Semiconductor Device Bonding Portion Void Reduction
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Solution Overview
Problem
The existing power semiconductor devices experience a reduction in connection reliability due to the accumulation of voids in the peripheral region of the bonding portion, which is formed from a sintering material with silver as the main component, leading to stress and potential cracking at the interface between the semiconductor element and the insulative substrate.
Innovation Solution
The semiconductor device incorporates a bonding portion with first and second sintered layers of varying densities, where the first sintered layers are denser and distributed within the bonding portion, and the second sintered layer surrounds them, formed through a two-stage sintering process to minimize voids and reduce stress during the sintering process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If sintering of metal particles progresses in the bonding portion, then the bonding strength increases, but voids gather in the peripheral region which lowers connection reliability
Solution Approach 1:
The patent applies local quality by creating different sintered layers with different densities at different locations within the bonding portion. The first sintered layer has higher density in the central region, while the second sintered layer has lower density in the peripheral region, optimizing each region's properties for its specific function.
Solution Approach 2:
The bonding portion is segmented into multiple sintered layers with different densities and compositions. This segmentation allows independent optimization of each layer's sintering characteristics, preventing void accumulation while maintaining overall bonding strength.
2Ease of manufacture
If sintering progresses uniformly throughout the bonding portion, then manufacturing simplicity is maintained, but voids accumulate at the periphery reducing connection reliability
Solution Approach 1:
The patent applies preliminary action by pre-forming the sintering material with a non-uniform density distribution before sintering. This preliminary structuring ensures that during subsequent sintering, voids are prevented from accumulating at the periphery, achieving reliable bonding without complex post-processing.
Solution Approach 2:
The patent changes the physical parameters of the sintering material, specifically the density distribution, to create a gradient structure. This parameter change allows the material to sinter uniformly while preventing void accumulation, maintaining manufacturing simplicity without sacrificing reliability.
3Device complexity
If a single uniform sintered layer is used in the bonding portion, then device complexity is reduced, but stress concentration occurs leading to potential cracking
Solution Approach 1:
The patent uses local quality by creating sintered layers with different densities at different locations. The higher density first sintered layer in the center and lower density second sintered layer at the periphery create a gradient structure that distributes stress evenly, preventing cracking while maintaining relatively simple device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the connection reliability between the semiconductor element and the insulative substrate by reducing voids and minimizing stress, thereby improving the bonding integrity and preventing cracking.
Implementation Method 1
the bonding portion includes first sintered layers distributed in the bonding portion and a second sintered layer having a density differing from that of each of the first sintered layers
Data Source
AI summary
A semiconductor device includes an insulative substrate, a wiring pattern, a bonding portion, and a semiconductor element. The wiring pattern is formed on an upper surface of the insulative substrate. The bonding portion is formed on an upper surface of the wiring pattern. The semiconductor element includes an electrode pad connected to an upper surface of the bonding portion. The bonding portion includes first sintered layers distributed in the bonding portion and a second sintered layer having a density differing from each of the first sintered layers and surrounding the first sintered layer.