Semiconductor Device Boosted Voltage Supply Circuit
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining signal waveform sharpness due to the influence of wiring parasitic resistance and load capacity, particularly in high-frequency operations, which can lead to data destruction and increased circuit area.
Innovation Solution
The semiconductor device incorporates a boosted voltage supply circuit and a boosting circuit with a capacitance coupling type voltage boosting mechanism, which generates a boosted potential and supplies it to the distal end of the signal wiring, thereby reducing the impact of parasitic resistance and load capacity on signal propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a constant voltage is supplied to the word line regardless of power supply voltage, then the word line can be driven at a constant voltage, but the circuit area increases due to additional boosting circuits
Solution Approach 1:
The patent divides the word line into multiple segments with different voltage supply strategies. The distal end receives boosted voltage through capacitive coupling while the proximal end is driven by conventional drive circuits, allowing localized improvement without global area increase.
Solution Approach 2:
The patent applies different voltage supply methods to different locations of the word line. The distal end receives boosted voltage to compensate for parasitic effects, while other portions use standard drive circuits, optimizing performance where needed without unnecessary area overhead.
2Reliability
If hierarchical word line structure is used, then data destruction can be prevented, but the circuit area increases due to coupling requirements
Solution Approach 1:
The patent implements a hierarchical word line structure that segments the word line into global and local portions. The global word line receives boosted voltage at its distal end while the local word line is driven conventionally, preventing data destruction without requiring full hierarchical coupling throughout the entire circuit.
3Productivity
If wiring length is increased to reach distal ends, then more cells can be accessed, but signal waveform unsharpness increases due to parasitic resistance
Solution Approach 1:
The patent applies preliminary action by charging the capacitive elements before the word line is actually needed. This pre-charging ensures that when the word line is activated, the boosted voltage is already available at the distal end, compensating for parasitic resistance effects before they can degrade the signal waveform.
Solution Approach 2:
The patent changes the voltage parameter at the distal end of the word line by using capacitive coupling to provide boosted voltage. This parameter change compensates for the voltage drop caused by parasitic resistance in long wirings, maintaining signal waveform sharpness while enabling access to more cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables faster operation speeds while maintaining signal integrity and preventing data disruption, without increasing the circuit area.
Implementation Method 1
a boosting circuit with a capacitance coupling type voltage boosting mechanism, which generates a boosted potential and supplies it to the distal end of the signal wiring
Data Source
AI summary
The semiconductor device includes a supply circuit for supplying a boosted voltage to a distal end of a wiring driven by a drive signal. The supply circuit includes an inverter circuit having an input coupled to the wiring, and a switch element controlled by an output signal of the inverter circuit. The switch element couples the boosted voltage to the distal end of the wiring.