Semiconductor Storage Boosting Circuits Area Reduction

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Solution Overview

Problem

Current semiconductor storage devices face challenges in reducing circuit area while maintaining efficient power generation and voltage regulation for NAND-type flash memory systems.

Innovation Solution

The implementation of a boosting circuit configuration using enhancement type N-type transistors as driver transistors, which reduces the circuit area by utilizing enhancement type transistors with higher threshold voltages, allowing for a smaller footprint compared to depletion type transistors, and includes a dual boosting circuit setup to efficiently generate and regulate voltages for the memory system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If depletion type transistors are used as driver transistors in boosting circuits, then the circuit can operate reliably, but the circuit area becomes larger

Engineering Contradiction:
Improvecircuit operation reliabilityVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The patent changes the threshold voltage parameter of the driver transistor by selecting enhancement type transistors with higher threshold voltages instead of depletion type transistors. This parameter change allows the transistor to function effectively as a driver in the boosting circuit while reducing the required circuit area, thereby resolving the contradiction between reliability and area.

Inventive Principle:
Principle #35Parameter changes

2Area of moving object

If enhancement type transistors with higher threshold voltages are used, then the circuit area is reduced, but the boosting capacity must be optimized

Engineering Contradiction:
Improvecircuit areaVSAvoidboosting capacity
Core Design Contradiction:
Area of moving objectVSPower

Solution Approach 1:

The patent applies local quality by using enhancement type transistors with higher threshold voltages specifically for the driver transistor position in the boosting circuit, while other transistors in the circuit may use different types. This localized optimization reduces the driver transistor area without compromising the overall boosting capacity of the circuit.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs multiple boosting circuits with different boosting capacities that can be dynamically selected based on operational requirements. This dynamic configuration allows the system to optimize between area and boosting capacity by activating only the necessary boosting circuits for each operating condition.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11551767B2Semiconductor storage device having boosting circuits with different boosting capacities
Publication Date: 2023.01.10 KIOXIA CORP
  • US11551767B2 patent drawing
  • US11551767B2 patent drawing
  • US11551767B2 patent drawing

AI summary

A semiconductor storage device includes a first boosting circuit, a second boosting circuit, a first driver circuit that is activated when a first output voltage generated by the first boosting circuit is supplied thereto, and a first driver transistor that is controlled by the first driver circuit and coupled between a power supply line and the second boosting circuit.