Semiconductor Bottom Electrode Capping Pattern for Structural Support

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Solution Overview

Problem

As semiconductor devices undergo increased integration density to achieve high operating speeds and low power consumption, they face challenges in maintaining electric characteristics and production yield due to deterioration in electric performance.

Innovation Solution

The semiconductor device design includes bottom electrodes with supporting patterns and a capping pattern that extends to cover side and top surfaces, along with a dielectric layer between electrodes, to enhance structural support and prevent damage during etching processes, thereby improving electric characteristics and production yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If integration density is increased to achieve high operating speeds and low power consumption, then operating performance is improved, but electric characteristics and production yield deteriorate

Engineering Contradiction:
Improveoperating speedVSAvoidelectric characteristics
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The device structure is segmented into multiple functional layers including bottom electrodes, dielectric layers, top electrodes, and capping patterns. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall device performance and reliability at high integration densities

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Capping patterns are formed in advance to cover and protect the side surfaces of bottom electrodes before subsequent processing steps. This preliminary protective action prevents electrode damage during manufacturing, ensuring production yield and electric characteristics are maintained even as integration density increases

Inventive Principle:
Principle #10Preliminary action

2Speed

If integration density is increased to achieve high operating speeds and low power consumption, then operating performance is improved, but production yield deteriorates

Engineering Contradiction:
Improveoperating speedVSAvoidproduction yield
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

Capping patterns are formed in advance to cover and protect the side surfaces of bottom electrodes before subsequent processing steps. This preliminary protective action prevents electrode damage during manufacturing, ensuring production yield and electric characteristics are maintained even as integration density increases

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The capping patterns serve as a protective cushion layer that absorbs mechanical stress and prevents damage to the underlying bottom electrodes during etching and other manufacturing processes. This beforehand cushioning ensures high production yield by preventing process-induced defects

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Stability of the object's composition

If supporting patterns are added to support bottom electrodes, then structural stability is improved, but device complexity increases

Engineering Contradiction:
Improvestructural stabilityVSAvoidstructure complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The capping patterns serve multiple functions simultaneously: they provide structural support to prevent electrode collapse, protect side surfaces during processing, and maintain structural stability. This multi-functionality reduces the need for separate supporting structures, thereby limiting the increase in device complexity while improving structural stability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230217647A1Semiconductor devices
Publication Date: 2023.07.06 SAMSUNG ELECTRONICS CO LTD
  • US20230217647A1 patent drawing
  • US20230217647A1 patent drawing
  • US20230217647A1 patent drawing

AI summary

A semiconductor device includes bottom electrodes on a substrate. A supporting pattern is disposed between the bottom electrodes in a plan view. A top electrode covers the bottom electrodes and the supporting pattern. A dielectric layer is disposed between the bottom electrodes and the top electrode and between the supporting pattern and the top electrode. A capping pattern is interposed between the bottom electrodes and the dielectric layer and between the supporting pattern and the dielectric layer. The capping pattern covers at least a portion of a side surface of the supporting pattern and extends to cover a top surface of the supporting pattern and top surfaces of the bottom electrodes.