Semiconductor Package Bridge Die Stack for Fine Vertical Interconnects
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Solution Overview
Problem
The existing use of copper posts in fan-out semiconductor packages is limited by the constraints of the photo and plating processes, leading to increased signal processing defects and difficulties in applying these posts to thicker packages.
Innovation Solution
The implementation of a bridge die stack that replaces copper posts, allowing for finer vertical interconnections by stacking multiple bridge dies with through-vias, which are electrically connected to the redistribution wiring layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If copper posts are used for vertical interconnection, then electrical connection between redistribution wiring layers is achieved, but the height of copper post is limited due to photo process and plating process constraints
Solution Approach 1:
The patent divides the vertical interconnection structure into multiple bridge dies stacked in sequence, where each bridge die contains through-vias. This segmentation allows the total height to be extended by adding more bridge dies, overcoming the height limitation of single copper posts while maintaining manufacturing precision through standardized bridge die structures.
Solution Approach 2:
The patent introduces bridge dies as intermediary components between the lower and upper redistribution wiring layers. These bridge dies act as mediator structures that provide fine vertical wiring capability, replacing the direct copper post approach and enabling better signal throughput through controlled impedance pathways.
2Length of moving object
If copper post height is increased, then vertical interconnection capability is improved, but signal processing defect rate increases
Solution Approach 1:
Instead of using a single tall copper post that increases defect rate, the patent segments the vertical connection into multiple shorter bridge dies. Each bridge die maintains optimal signal characteristics, and the stacked configuration achieves the required total height without compromising signal integrity or increasing defect rates.
Solution Approach 2:
The patent changes the structural parameters of the vertical interconnection by transitioning from a monolithic copper post to a modular bridge die stack. This parameter change allows control over impedance, signal quality, and height independently, improving reliability while achieving the necessary vertical extent.
3Length of stationary object
If package thickness increases, then more vertical interconnection is needed, but copper posts become difficult to apply
Solution Approach 1:
The patent employs segmented bridge dies that can be stacked in varying numbers according to the required package thickness. This modular approach allows easy adaptation to different thickness requirements without changing the fundamental manufacturing process, unlike copper posts which become difficult to apply as thickness increases.
Solution Approach 2:
The bridge die structure serves as a universal solution for vertical interconnection across different package thicknesses. By simply adjusting the number of bridge dies in the stack, the same manufacturing approach can accommodate varying thickness requirements, providing multi-functionality that copper posts lack.
Data Source
AI summary
A semiconductor package includes a lower redistribution wiring layer having first redistribution wirings, the lower redistribution wiring layer having a first region and a second region surrounding the first region, a semiconductor chip on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings, at least one bridge die stack on the second region of the lower redistribution wiring layer and including a plurality of bridge dies sequentially stacked on one another, each of the bridge dies including a plurality of through-vias that are electrically connected to the first redistribution wirings, a sealing member on the lower redistribution wiring layer covering the semiconductor chip and the at least one bridge die stack and an upper redistribution wiring layer on the sealing member and including second redistribution wirings electrically connected to the through-vias of the at least one bridge die stack.