Semiconductor Bridge Packaging With Embedded Passives for Lower Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of multiple semiconductor devices in miniaturized electronic devices poses challenges due to the need for advanced packaging and assembling techniques that enhance electrical performance and reduce transmission and insertion losses.
Innovation Solution
A semiconductor packaging method involving a carrier with semiconductor dies, encapsulant, inner and outer redistribution layers, and semiconductor bridges, which allows for efficient electrical connection and integration of passive devices within a bridging layer, enabling shorter connection paths and increased efficiency without substantial thickness increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor devices are integrated in miniaturized electronic devices, then device functionality and electrical performance are improved, but transmission loss and insertion loss increase
Solution Approach 1:
The patent transitions from planar 2D interconnection to 3D vertical interconnection by stacking semiconductor dies with redistribution layers and via holes. This dimensional change shortens current paths and reduces signal transmission distance, thereby lowering transmission loss while maintaining high device integration density.
Solution Approach 2:
The patent embeds passive devices (capacitors, inductors, resistors) within the redistribution layers and between semiconductor dies in the 3D stack. This nesting approach integrates additional functionality without increasing the device footprint, allowing multiple devices to coexist while minimizing signal path length and energy loss.
2Reliability
If advanced packaging techniques are used to integrate multiple semiconductor devices, then electrical performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor package into discrete functional layers including individual semiconductor dies, redistribution layers, passive device layers, and encapsulant layers. Each layer can be independently fabricated, tested, and assembled, which simplifies the overall manufacturing process despite the 3D complexity by enabling modular production and reducing process interdependence.
3Loss of energy
If connection paths between semiconductor devices are shortened, then transmission loss is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms via holes, conductive plugs, and redistribution layer patterns before assembling the semiconductor dies. This preliminary preparation of interconnection structures on each die individually allows for precise alignment during assembly, as the alignment marks and positioning features are already in place, reducing the actual alignment precision requirements during the bonding process.
Data Source
AI summary
A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.