Semiconductor Package Bridge Layout for Multi-Die Memory Links
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Solution Overview
Problem
The existing semiconductor package manufacturing methods are limited by the need for multiple bridge chips to connect semiconductor memory devices to logic devices, leading to increased production costs and space constraints due to the sequential stacking of chips.
Innovation Solution
A semiconductor package design that uses a single bridge chip to electrically connect multiple semiconductor memory devices and logic devices through a redistribution wiring layer, eliminating the need for additional bridge chips and optimizing space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple bridge chips are used to connect semiconductor memory devices to logic devices, then electrical connection reliability is improved, but production cost and device complexity increase
Solution Approach 1:
Multiple bridge chips are merged into a single bridge chip that electrically connects multiple semiconductor memory devices to the logic device. The bridge chip includes multiple connection interfaces that can simultaneously connect to multiple memory devices, eliminating the need for separate bridge chips for each memory device while maintaining reliable electrical connections.
Solution Approach 2:
The bridge chip is designed with multi-functionality to serve multiple connection purposes. It can simultaneously establish electrical connections between the logic device and multiple different semiconductor memory devices through its multiple interfaces, making a single component perform the function previously requiring multiple specialized components.
2Reliability
If multiple bridge chips are used to connect semiconductor memory devices to logic devices, then electrical connection capability is improved, but manufacturing cost increases
Solution Approach 1:
Multiple bridge chips are consolidated into one unified bridge chip structure, reducing the total component count. This merging reduces manufacturing costs by decreasing the number of individual chips that need to be produced, tested, and assembled, while still providing the necessary electrical connection capabilities to multiple memory devices.
Solution Approach 2:
The bridge chip is designed as a universal component that can interface with multiple types of semiconductor memory devices simultaneously. This multi-functional design allows for standardized manufacturing processes and reduces the need for device-specific bridge chips, thereby lowering overall production costs while maintaining comprehensive electrical connection capability.
3Reliability
If multiple bridge chips are used to connect semiconductor memory devices to logic devices, then connection capability is improved, but space utilization deteriorates
Solution Approach 1:
Multiple bridge chips are merged into a single integrated bridge chip that occupies less space than multiple separate chips would require. The unified structure consolidates multiple connection interfaces into one component, reducing the total area needed on the substrate while maintaining the capability to connect to multiple memory devices simultaneously.
Solution Approach 2:
The bridge chip utilizes three-dimensional stacking or multi-layer routing to provide multiple connection interfaces within a compact footprint. By transitioning from a two-dimensional layout of multiple separate chips to a vertically integrated or multi-layered single chip structure, the design achieves improved space utilization while preserving comprehensive connection capability.
Data Source
AI summary
A semiconductor package includes a substrate structure having a bridge chip therein; a semiconductor memory device on a first upper surface of the substrate structure and electrically connected to the bridge chip; and a semiconductor logic device on the first upper surface of the substrate structure and spaced apart from the semiconductor memory device, and the semiconductor logic device electrically connected to the bridge chip. The semiconductor memory device may include a redistribution wiring layer on the substrate structure and having a plurality of redistribution wirings; a plurality of buffer dies on a second upper surface of the redistribution wiring layer and electrically connected to the bridge chip through the plurality of redistribution wirings; and a plurality of semiconductor chips sequentially stacked on each of the plurality of buffer dies and electrically connected to the plurality of buffer dies.