Semiconductor Package Bridge Layout for Shorter Signal Paths
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Solution Overview
Problem
The challenge of integrating multiple semiconductor devices in miniaturized electronic apparatus while ensuring lower transmission and insertion losses, and improving electrical performance has not been adequately addressed by existing packaging and assembling techniques.
Innovation Solution
A semiconductor package structure is developed with a bridging layer that embeds semiconductor bridges and integrated passive devices, connected through through-vias and redistribution layers, allowing for efficient electrical connections and reduced connection distances without increasing package thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor devices are integrated in miniaturized electronic apparatus, then device functionality and electrical performance are improved, but transmission loss and insertion loss increase
Solution Approach 1:
The patent transitions from planar 2D packaging to 3D vertical integration by stacking semiconductor dies and passive devices in multiple layers connected through vertical vias and through-silicon vias (TSVs). This dimensional change enables shorter signal paths and better electrical performance while maintaining miniaturization, as signals travel vertically through the stack rather than laterally across large areas, reducing transmission and insertion losses.
Solution Approach 2:
The patent embeds passive devices (capacitors, inductors, resistors) within the semiconductor package structure itself, nesting them between or around active semiconductor dies. This nesting approach integrates multiple functional elements into a compact 3D arrangement, enabling better electrical performance and reduced signal path lengths without increasing the overall package footprint, thereby reducing transmission and insertion losses.
2Loss of energy
If connection distances are minimized to improve electrical performance, then transmission loss is reduced, but package thickness increases
Solution Approach 1:
The patent divides the package into multiple thin layers or tiers, with each layer containing specific devices or interconnect structures. By segmenting the package vertically into manageable layers connected by vias, the design achieves short connection distances within each layer while distributing the overall thickness across multiple segments, preventing any single layer from becoming excessively thick and managing heat dissipation more effectively.
Solution Approach 2:
The patent utilizes vertical stacking in the third dimension to achieve short horizontal connection distances. By routing signals vertically through TSVs and inter-layer vias rather than laterally across the substrate, the design minimizes transmission loss while the layered architecture allows precise control over overall package thickness, balancing electrical performance with mechanical constraints.
3Productivity
If wafer-level packaging is used to improve productivity, then manufacturing efficiency increases, but integration of multiple semiconductor devices becomes challenging
Solution Approach 1:
The patent employs a universal wafer-level packaging platform that can accommodate multiple types of semiconductor devices and passive components simultaneously. The standardized wafer-scale process supports integration of active dies, passive devices, and interconnect structures using common fabrication techniques (deposition, etching, vias), enabling high-volume manufacturing of complex multi-device packages without requiring device-specific process variations, thus maintaining productivity while handling complexity.
Solution Approach 2:
The patent combines multiple semiconductor devices, passive components, and interconnect structures into a single integrated wafer-scale package unit. By merging these diverse elements into one cohesive structure that can be processed and tested at the wafer level before final assembly, the design achieves high manufacturing efficiency while managing device complexity through unified processing and standardized integration architectures.
Data Source
AI summary
A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.