Semiconductor Package Bridge Vias for High-Density Chip Interconnects

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Solution Overview

Problem

Existing semiconductor packages face challenges in achieving high reliability, integration, and miniaturization while ensuring efficient electrical signal transmission between semiconductor chips.

Innovation Solution

The semiconductor package design includes a first substrate with a first lower semiconductor chip and bridge structures, a second substrate on top of the first lower chip and bridge structures, and first upper semiconductor chips on the second substrate, with conductive vias in the bridge structures for electrical connection between the chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If semiconductor chips are mounted on a printed circuit board using bonding wires or bumps, then electrical connection is achieved, but signal transmission speed and bandwidth density are limited

Engineering Contradiction:

Improvesignal transmission speedVSAvoidconnection reliability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent replaces traditional mechanical bonding methods (bonding wires and bumps) with direct chip-to-chip electrical connection structures. The connection structure includes contact portions that directly contact the chips, eliminating the need for intermediate bonding materials and mechanical connections, thereby improving signal transmission speed while maintaining connection reliability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If multiple semiconductor chips are integrated in a package, then functionality and performance are enhanced, but package size increases

Engineering Contradiction:

Improvechip integration capabilityVSAvoidpackage volume

Core Design Contradiction:

ProductivityVSVolume of moving object

Solution Approach 1:

The patent transitions from a planar two-dimensional arrangement of chips to a three-dimensional stacked configuration. Multiple chips are arranged in different layers (first chip in first layer, second chip in second layer), allowing higher integration density without proportionally increasing package footprint, thus improving productivity while controlling volume.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where connection structures are embedded within the package layers. The first connection structure is disposed between the first and second chips, and the second connection structure is disposed between the second and third chips, creating a compact nested arrangement that maximizes space utilization and enables high integration without excessive volume increase.

Inventive Principle:

Principle #7Nested doll (Nesting)

3Volume of moving object

If chips are placed closer together for miniaturization, then package size is reduced, but manufacturing precision requirements increase

Engineering Contradiction:

Improvepackage volumeVSAvoidchip placement precision

Core Design Contradiction:

Volume of moving objectVSManufacturing precision

Solution Approach 1:

The patent introduces connection structures as intermediary elements between adjacent chips. These connection structures include contact portions that precisely contact the chips and extend to connection pads, acting as mediators that facilitate accurate electrical connection even when chips are placed in close proximity, thereby enabling miniaturization without excessively increasing manufacturing precision requirements.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Productivity

If signal transmission paths are lengthened for higher integration, then more chips can be connected, but signal latency increases

Engineering Contradiction:

Improvechip connectivityVSAvoidsignal latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent optimizes the local quality of signal transmission paths by designing connection structures with conductive materials and configurations that minimize resistance and inductance. The connection structures include contact portions and connection pads arranged to create short, direct electrical paths, ensuring high-speed signal transmission even as more chips are integrated into the package.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250038112A1Semiconductor package including a plurality of semiconductor chips

Publication Date: 2025.01.30 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes a first substrate. A first lower semiconductor chip is disposed on the first substrate. A bridge structure is laterally spaced apart from the first lower semiconductor chip, on the first substrate. A second substrate is disposed on the first lower semiconductor chip and the bridge structure. A first upper semiconductor chip is disposed on the second substrate. The first upper semiconductor chip is spaced apart from the first lower semiconductor chip in a plan view. The bridge structure includes a base structure. Conductive vias are disposed in the base structure and are in contact with the first substrate. The first upper semiconductor chip is electrically connected to the first lower semiconductor chip through the conductive vias.