Semiconductor Device Bridge Wiring Power Supply Impedance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The stability of power supply voltage in semiconductor chips is challenging due to limitations in increasing the number of external terminals and the impedance of power supply wiring, which is difficult to reduce without modifying the manufacturing process or increasing costs.
Innovation Solution
A semiconductor device with a wiring structure that includes bridge wiring connecting second pad electrodes within the semiconductor chip, reducing the impedance of power supply wiring without requiring changes to the manufacturing process or increasing the number of external terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of external terminals for power supply is increased, then the stability of power supply voltage is improved, but the number of external terminals is determined by standards and cannot be freely increased
Solution Approach 1:
The invention transitions from increasing the number of external terminals (one-dimensional approach) to adding wiring layers within the semiconductor chip (moving to another dimension - internal wiring structure). By forming additional power supply wiring patterns in upper or lower wiring layers, the patent achieves improved power supply stability without being constrained by external terminal limitations imposed by standards.
2Reliability
If the cross-sectional area of power supply wiring is increased, then the impedance is reduced, but the manufacturing process must be changed which is not practical from cost point of view
Solution Approach 1:
The invention segments the power supply wiring into multiple separate wiring patterns distributed across different wiring layers. Instead of modifying a single wiring pattern's cross-sectional area (which would require process changes), the patent creates multiple wiring paths that collectively reduce impedance. This approach uses existing manufacturing capabilities to form multiple thinner wiring layers rather than changing the process to create fewer thicker wires.
Solution Approach 2:
The patent utilizes the third dimension (vertical stacking of wiring layers) to reduce impedance. By forming power supply wiring patterns in both upper and lower wiring layers relative to the semiconductor chip, the effective cross-sectional area for current flow is increased without modifying the manufacturing process for individual wiring layers, thus avoiding additional costs.
3Reliability
If the number of wiring layers for power supply is increased, then the impedance is reduced, but a new mask pattern must be formed which increases cost
Solution Approach 1:
The invention makes existing wiring layers serve multiple functions. The upper and lower wiring layers, which may have been designed for general signal or power distribution, are configured to specifically function as power supply wiring. This multi-functionality allows the patent to reduce impedance by utilizing existing wiring layer structures without requiring additional mask patterns or increasing device complexity beyond the original design.
Data Source
AI summary
In one semiconductor device, a semiconductor chip has first and second pad electrodes disposed on the main surface thereof, insulating films that cover the main surface of the semiconductor chip, a rewiring layer that is disposed between the insulating films, and a plurality of external terminals disposed on the top of the insulating film. The plane size of the first pad electrode and the second pad electrode differ from one another, and the first pad electrode and the second pad electrode are connected to any of the plurality of external terminals via the rewiring layer.