Semiconductor Die Brim Structure for Warpage-Resistant Bonding

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor structures face challenges in establishing reliable bonding and electrical inter-connection due to warpage issues, particularly in large size dies, which can lead to non-bonding problems during assembly.

Innovation Solution

A pruning process is applied to remove the peripheral portion of semiconductor dies to counteract warpage, followed by an enfolding process with gap-filling materials to stabilize the structure, ensuring planarity and effective bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If large size dies are used in semiconductor structures, then the area and functionality are improved, but warpage issues occur leading to non-bonding problems

Engineering Contradiction:
Improvedie areaVSAvoidbonding reliability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent extracts and removes the peripheral portion of the semiconductor die through a pruning process. This extraction eliminates the warpage-prone edge regions while retaining the functional core area, thereby resolving the contradiction between maintaining large die area and ensuring bonding reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The pruning process is performed preliminarily before bonding to counteract potential warpage issues. By removing peripheral portions in advance, the structure is pre-conditioned to prevent warpage-induced non-bonding problems during the bonding process.

Inventive Principle:
Principle #9Preliminary anti-action

2Reliability

If peripheral portions of semiconductor dies are removed to reduce warpage, then bonding reliability is improved, but the die area is reduced

Engineering Contradiction:
Improvebonding reliabilityVSAvoiddie area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by differentiating the treatment of different die regions. The peripheral portions are removed while the central functional area is preserved, creating a structure with non-uniform geometry that optimizes bonding reliability in critical regions while maintaining overall die functionality.

Inventive Principle:
Principle #3Local quality

3Reliability

If gap-filling materials are added to stabilize the structure, then planarity and bonding reliability are improved, but the device complexity increases

Engineering Contradiction:
Improvebonding reliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces gap-filling materials as intermediary substances between the pruned die and the bonding partner. These materials act as mediators that fill voids and accommodate dimensional mismatches, thereby ensuring planarity and bonding reliability without requiring complex structural modifications to the die itself.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260053051A1Semiconductor structure and manufacturing method thereof
Publication Date: 2026.02.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260053051A1 patent drawing
  • US20260053051A1 patent drawing
  • US20260053051A1 patent drawing

AI summary

A semiconductor structure, including a first semiconductor structure, a second semiconductor structure, and a filling material is disclosed. The first semiconductor structure has a first surface and a second surface opposite to the first surface. The first semiconductor structure has a body portion and a semiconductor brim portion protruded from the body portion. The semiconductor brim portion is closer to the second surface. The second semiconductor structure is in contact with the first surface of the first semiconductor structure and bonded with the first semiconductor structure. The filling material surrounds the first semiconductor structure and is filled between the semiconductor brim portion and the second semiconductor structure. The filling material wraps around and covers the semiconductor brim portion, and a sidewall of the filling material is aligned with a sidewall of the second semiconductor structure.