Semiconductor Structure With Buffer Cavity for Wafer Warpage Relief
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Solution Overview
Problem
The current semiconductor production processes face warpage issues due to differences in thermal expansion coefficients between film-layer materials and substrate materials, leading to residual stress and deformation during high-temperature treatments, which are difficult to address at the front-end-of-line stage.
Innovation Solution
A semiconductor structure is designed with an accommodation recess in the substrate's non-die region, filled with a buffer material having a thermal expansion coefficient close to that of the substrate, and a passivation layer with a through-via communication, allowing the buffer cavity to buffer thermal stress and alleviate warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If film-layer materials with different thermal expansion coefficients are deposited on the substrate, then functional performance is improved, but warpage and residual stress occur during high-temperature treatment
Solution Approach 1:
The patent introduces a buffer layer with specific thermal expansion properties at the interface between the substrate and film layers. This buffer layer has a thermal expansion coefficient that is lower than that of the substrate, creating a gradient structure that locally compensates for thermal stress. The buffer layer is positioned specifically in regions where thermal stress accumulates, allowing different parts of the structure to have different thermal compensation characteristics.
Solution Approach 2:
The patent employs a composite structure consisting of the substrate, buffer layer, and film layers. The buffer layer is made of a material with specific thermal properties that differ from both the substrate and the film layers. This composite material approach allows the system to combine the advantages of different materials: the substrate provides mechanical support, the buffer layer provides thermal stress compensation, and the film layers provide functional performance.
2Adaptability or versatility
If multiple film layers are added to improve functionality, then device performance is enhanced, but thermal stress and warpage increase
Solution Approach 1:
The buffer layer is strategically positioned at the substrate interface where thermal stress originates. By placing the buffer layer with lower thermal expansion coefficient at this critical location, the patent creates a local stress-compensating zone that prevents stress propagation through the entire multi-layer structure. This local intervention allows multiple functional layers to be added without proportionally increasing overall thermal stress.
3Ease of manufacture
If conventional deposition processes are used, then manufacturing simplicity is maintained, but warpage occurs during high-temperature treatment
Solution Approach 1:
The buffer layer is deposited on the substrate before the functional film layers are added. This preliminary action of creating the buffer layer first allows it to serve as a stress-compensating foundation that prevents warpage from developing during subsequent high-temperature processing. The buffer layer is in place beforehand to counteract thermal stress before the functional layers are deposited and before any high-temperature treatment occurs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces thermal stress impact on the semiconductor structure, improving production yield and performance by timely release of thermal stress and preventing warpage deformation.
Implementation Method 1
there are differences between parameters such as the coefficients of thermal expansion of the various film-layer materials deposited on the substrate during the production process and parameters such as the coefficient of thermal expansion of the substrate materials, and thus the wafer is subject to warpage upon various high-temperature treatment processes
Data Source
AI summary
Provided is a semiconductor structure. The semiconductor structure includes a substrate including a die region and a non-die region, wherein an accommodation recess is formed in a side of the substrate and positioned in the non-die region; a buffer disposed in the accommodation recess; a functional film layer disposed on the side, where the accommodation recess is formed, of the substrate; and a passivation layer covering the functional film layer and the substrate. A buffer cavity with an opening facing away from the substrate is formed in the buffer. An orthographic projection of the functional film layer on the substrate is within the die region. A first through-via is formed in the passivation layer. An orthographic projection of the first through-via on the substrate is at least partially overlapped with an orthographic projection of the opening on the substrate. The opening is in communication with the first through-via.