Semiconductor Package Buffer Layer Stress Absorption
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving small size and low cost while protecting dies from damage, with traditional wafer level packaging methods being expensive and resulting in thick packages.
Innovation Solution
The solution involves forming signal and ground leads directly under the die, incorporating a buffer layer to absorb stress, and using a molding portion on the buffer layer to prevent damage and parasitic effects, eliminating the need for a cap wafer and air cavity, thereby reducing size and production cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cap wafer is bonded on the MMIC wafer to form an air cavity for die protection, then the die is protected from damage, but the production cost increases and the package thickness becomes large
Solution Approach 1:
The patent extracts and eliminates the cap wafer and air cavity structure from the packaging process. Instead of bonding a cap wafer to form an air cavity for die protection, the invention uses a molding compound that directly contacts and protects the die, removing the unnecessary intermediate structures and reducing manufacturing complexity and cost.
Solution Approach 2:
The patent merges the die protection function with the molding compound. The molding compound serves dual purposes: it encapsulates and protects the die while also providing the package structure, eliminating the need for separate cap wafer and air cavity components, thereby reducing production cost and package thickness.
2Reliability
If a cap wafer is bonded on the MMIC wafer to form an air cavity for die protection, then the die is protected from damage, but the package thickness becomes large
Solution Approach 1:
The patent removes the cap wafer and air cavity structures that contribute to package thickness. By using a molding compound that directly encapsulates the die, the invention eliminates the vertical space required for cap wafer bonding and air cavity formation, thereby reducing overall package thickness while maintaining die protection.
Solution Approach 2:
The patent combines the protective function into the molding compound layer, which directly contacts and protects the die. This merged structure eliminates the need for separate protective layers (cap wafer and air cavity), significantly reducing the package thickness while ensuring die protection during handling and operation.
3Device complexity
If the molding compound directly contacts the die, then the package structure is simplified, but unwanted parasitic effects and loss occur
Solution Approach 1:
The patent introduces a buffer layer as an intermediary between the die and the molding compound. This buffer layer prevents direct contact between the molding compound and the die, thereby eliminating unwanted parasitic effects and signal loss while still providing mechanical support and stress relief. The buffer layer acts as a mediator that maintains electrical isolation while allowing structural integration.
4Area of stationary object
If signal leads and ground leads are formed directly under the die, then the package size is reduced, but the manufacturing precision requirement increases
Solution Approach 1:
The patent forms the signal leads and ground leads directly on the die before the die is mounted in the package. This preliminary formation of leads on the die itself eliminates the need for separate lead formation steps in the final package assembly, reducing the overall package size while managing manufacturing precision requirements through integrated processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the thickness and production cost of semiconductor packages, enhances RF performance by preventing unwanted parasitic effects, and allows for smaller package sizes without compromising die protection.
Implementation Method 1
a buffer layer, formed on the die, configured to absorb a stress applied to the die and prevent the die from damage and prevent to contact to molding to generate unwanted parasitic effect and loss
Data Source
AI summary
A semiconductor package includes a die comprising at least a via and a least a hot via; a ground lead, formed directly under a back side of the die, contacting with the back side of the die, and directly connected to the a least a hot via and the at least a via of the die; a buffer layer, formed on the die, configured to absorb a stress applied to the die and prevent the die from damage; and a molding portion, formed on the die buffer layer.