Semiconductor Package Buffer Layer for Thermal Stress Cracking
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving reliable connections and protection for semiconductor chips due to limitations in microbump formation and underfill materials, which can lead to mechanical stress and reliability issues under thermal conditions.
Innovation Solution
The semiconductor package incorporates a buffer layer with a lower elastic modulus than the underfill portion and encapsulant, which covers the dam structure and underfill portions, enhancing mechanical protection and preventing cracks during thermal processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If an underfill portion is formed to physically protect microbumps, then mechanical protection is improved, but mechanical stress accumulates under thermal conditions leading to reliability issues
Solution Approach 1:
A buffer layer is introduced as an intermediary component between the underfill portion and the encapsulant. This buffer layer has a lower elastic modulus than both the underfill portion and the encapsulant, serving as a stress-absorbing mediator that prevents stress concentration at the interface between the underfill portion and encapsulant, thereby maintaining reliability under thermal conditions while preserving mechanical protection.
Solution Approach 2:
The elastic modulus parameter is strategically varied across different layers: the buffer layer is designed with a lower elastic modulus than both the underfill portion and the encapsulant. This parameter change creates a gradient structure that gradually transitions stress, preventing sudden stress concentration and crack formation while maintaining the mechanical protection function of the underfill portion.
2Strength
If rigid encapsulant material is used to protect the semiconductor chip, then mechanical strength is improved, but thermal stress causes cracks in the underfill portion
Solution Approach 1:
The buffer layer is positioned beforehand between the rigid encapsulant and the underfill portion to provide cushioning against thermal stress. This pre-positioned cushioning layer absorbs and distributes thermal stress before it can concentrate at the interface and cause cracks in the underfill portion, while allowing the encapsulant to maintain its protective mechanical strength.
Solution Approach 2:
The elastic modulus parameter is changed by introducing the buffer layer with lower elasticity between the rigid encapsulant and the underfill portion. This parameter variation creates a compliant interface that accommodates thermal expansion differences, preventing crack formation in the underfill portion while preserving the overall mechanical strength provided by the encapsulant.
3Reliability
If microbumps are formed to electrically connect the semiconductor chip to the substrate, then electrical connection is improved, but mechanical stress concentrates at the microbump interface
Solution Approach 1:
The buffer layer serves as an intermediary between the underfill portion (which protects the microbumps) and the encapsulant. This intermediary layer distributes mechanical stress away from the microbump interface, reducing stress concentration at the electrical connection points while maintaining the integrity of the electrical connection through the microbumps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly improves the reliability of the semiconductor package by reducing mechanical stress and preventing cracks in the underfill portions, thereby ensuring consistent performance under varying thermal conditions.
Implementation Method 1
the buffer layer includes a material having an elastic modulus lower than an elastic modulus of the underfill portion and an elastic modulus of the encapsulant
Data Source
AI summary
A semiconductor package includes a package substrate, an interposer on the package substrate, electrically connected to the package substrate, a first chip structure including a first semiconductor chip, first microbumps electrically connecting the first semiconductor chip to the interposer, and a first underfill portion on the interposer and respectively covering the first microbumps, a second chip structure including a second semiconductor chip spaced apart from the first semiconductor chip, second microbumps electrically connecting the second semiconductor chip to the interposer, and a second underfill portion on the interposer and respectively covering the second microbumps, a dam structure on the interposer and surrounding at least a portion of each of the first and second underfill portions, a buffer layer on the interposer, and covering at least portions of the dam structure, the first underfill portion, and the second underfill portion, and an encapsulant covering the buffer layer.