Semiconductor Device Buffer Layer for Dopant Diffusion Control

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Solution Overview

Problem

Dopants from the source/drain region of fin-based transistors, such as finFETs and nanostructure transistors, diffuse into the mesa region, leading to increased electron tunneling, short channel effects, and leakage, which degrade device performance.

Innovation Solution

A buffer layer is formed under the source/drain region with a curved top surface and specific dimensions to prevent dopant diffusion, reducing leakage and short channel effects by fully covering the mesa region and isolating it from the source/drain region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If source/drain region is formed adjacent to fin structure, then transistor functionality is achieved, but dopant diffusion into mesa region increases leakage and short channel effects

Engineering Contradiction:
Improvetransistor functionalityVSAvoidleakage current
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

A buffer layer is introduced as an intermediary structure between the source/drain region and the mesa region. This buffer layer acts as a barrier that prevents dopant diffusion from the source/drain region into the mesa region, thereby reducing leakage current and short channel effects while maintaining the functional integrity of the transistor.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The structure is segmented into distinct regions: source/drain region, buffer layer, and mesa region. By dividing the continuous structure into separate segments with the buffer layer in between, dopant diffusion pathways are interrupted, preventing harmful diffusion into the mesa region while preserving transistor operation.

Inventive Principle:
Principle #1Segmentation

2Reliability

If buffer layer is added to block dopant diffusion, then leakage is reduced, but device structure becomes more complex

Engineering Contradiction:
Improveleakage currentVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The buffer layer is implemented as a thin film or shell-like structure that provides effective dopant blocking with minimal added complexity. The thin-film nature allows it to be integrated into existing transistor structures without significantly increasing overall device complexity or footprint.

Inventive Principle:
Principle #30Flexible shells and thin films

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The buffer layer effectively blocks dopant diffusion, enhancing device performance by decreasing off-current and leakage, and minimizing short channel effects, thereby improving the overall functionality of the transistors.

Implementation Method 1

Dopants from the source/drain region of fin-based transistors, such as finFETs and nanostructure transistors, diffuse into the mesa region. A buffer layer is formed under the source/drain region with a curved top surface and specific dimensions to prevent dopant diffusion

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS12356681B2Semiconductor device and methods of manufacturing
Publication Date: 2025.07.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12356681B2 patent drawing
  • US12356681B2 patent drawing
  • US12356681B2 patent drawing

AI summary

In some implementations, a buffer layer is formed under a source/drain region of a device. A shape of the buffer layer may include a curved top surface having a height that extends to increase coverage of nanosheets of a fin structure of the device. The shape also includes regions having widths that extend towards shallow trench isolation regions of the device. The shape reduces a likelihood of dopants diffusing from the source/drain region into a mesa region of the fin structure. As a result, a performance of the device may be increased by decreasing short channel effects, decreasing an off-current of the device, and decreasing leakage within the device, among other examples.