Semiconductor Patterning With Buffer Layers for Defect-Reduced Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of forming active patterns with different densities and widths in semiconductor devices, particularly in highly integrated semiconductor devices, is that it is difficult to achieve precise patterning without defects.
Innovation Solution
A method involving the sequential stacking of a mask layer, buffer layer, and mandrel layers on a substrate, with the use of spacers and mandrel patterns to facilitate precise etching, reducing defects by using a buffer layer with lower electrical conductivity to mitigate electromagnetic forces and enhance etching selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single etching process is used to form both first and second active patterns, then the process is simple, but the patterning precision deteriorates due to different pattern densities and widths
Solution Approach 1:
The etching process is segmented into two separate etching processes: a first etching process for forming first active patterns in the first region, and a second etching process for forming second active patterns in the second region. This segmentation allows each etching process to be optimized for its specific pattern requirements, thereby maintaining high patterning precision while managing process complexity
Solution Approach 2:
Different etching conditions and parameters are applied to different regions of the substrate. The first etching process uses parameters optimized for the high-density first active patterns, while the second etching process uses parameters optimized for the different-density second active patterns. This local optimization ensures high patterning precision for both regions
2Device complexity
If spacers are formed close to highly conductive mask layers, then the device structure is compact, but electromagnetic forces cause spacer bending and process defects
Solution Approach 1:
A buffer layer with lower electrical conductivity is introduced between the highly conductive mask layer and the spacer. This buffer layer acts as an intermediary that reduces the electromagnetic forces generated by the conductive mask layer, thereby preventing spacer bending and reducing process defects while maintaining the compact device structure
Solution Approach 2:
The device structure uses a composite material approach by combining materials with different electrical conductivities. The mask layer uses a highly conductive material for its primary function, while the buffer layer uses a material with lower electrical conductivity to mitigate electromagnetic effects. This composite structure balances electrical performance with mechanical stability
3Ease of manufacture
If etching selectivity between buffer layer and mask layer is low, then the etching process is simple, but the pattern formation precision deteriorates
Solution Approach 1:
The etching process parameters are optimized to achieve high etching selectivity between the buffer layer and mask layer. By adjusting parameters such as etching chemistry, temperature, and power, the etching process selectively removes the buffer layer while preserving the mask layer, thereby achieving precise pattern formation without requiring complex process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces process defects by minimizing spacer bending and ensuring high etching selectivity, resulting in active patterns with excellent side wall profiles and reduced defects.
Implementation Method 1
the buffer layer may be disposed on an etching target layer, so that an electromagnetic force generated by high electrical conductivity of the etching target layer can be reduced so as to reduce a defect in which the spacer is bent
Implementation Method 2
The buffer layer includes a material having lower electrical conductivity than the mask layer and having etching selectivity with respect to the mask layer
Data Source
AI summary
Provided is a method for manufacturing a semiconductor device, in which a mask layer, a buffer layer, and a first mandrel layer are sequentially stacked on a substrate including a first region and a second region. First mandrel patterns are formed on the buffer layer in the first region, and a second mandrel pattern covering the buffer layer in the second region is formed. A first spacer contacting side walls of the first mandrel pattern and the second mandrel pattern is formed on the buffer layer. The first mandrel patterns are removed. A buffer layer pattern and a preliminary mask pattern are formed on the substrate. The second mandrel pattern is removed. In addition, a mask pattern is formed. The buffer layer includes a material having lower electrical conductivity than the mask layer and having etching selectivity with respect to the mask layer.