Semiconductor Buffer Layer Carrier Gradient Control
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Solution Overview
Problem
Conventional semiconductor devices face challenges with steep carrier concentration gradients between the n−-type drift layer and n-type buffer layer, leading to snap-off and radiofrequency oscillation, as well as reduced avalanche tolerance and maximum controllable current density, due to the reliance on lifetime control methods which are sensitive to irradiation conditions and temperature.
Innovation Solution
A semiconductor device with an n-type drift layer, a p-type anode layer, and an n-type cathode layer, featuring an n-type buffer layer with a peak impurity concentration higher than the drift layer but lower than the cathode layer, and a carrier concentration gradient of 20 to 2000 cm−4, which helps in controlling the VF-EREC trade-off characteristic without relying on lifetime control methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a steep carrier concentration gradient is used between the n−-type drift layer and n-type buffer layer, then the device structure is simpler, but snap-off and radiofrequency oscillation occur
Solution Approach 1:
The patent applies local quality by creating a buffer layer with a specific intermediate carrier concentration between the n−-type drift layer and n-type cathode layer. This buffer layer has a carrier concentration that is higher than the drift layer but lower than the cathode layer, forming a gradual transition zone that locally modifies the electric field distribution to prevent snap-off and radiofrequency oscillation.
2Reliability
If lifetime control methods are used to improve recovery characteristics, then the reverse recovery behavior is improved, but the manufacturing precision is reduced due to sensitivity to irradiation conditions and temperature
Solution Approach 1:
The patent changes the fundamental parameter approach from lifetime control (which requires precise control of irradiation conditions and temperature) to carrier concentration gradient control. By designing the buffer layer with a specific carrier concentration range (higher than drift layer, lower than cathode layer), the invention achieves reverse recovery improvement through a more robust parameter that is less sensitive to manufacturing variations.
3Ease of manufacture
If a conventional buffer layer structure is used, then the device is easier to manufacture, but EMI noise and breakdown tolerance are compromised
Solution Approach 1:
The patent changes the carrier concentration parameter in the buffer layer to an intermediate value between the drift layer and cathode layer. This parameter change creates a gradual carrier concentration gradient that reduces EMI noise and improves breakdown tolerance while maintaining manufacturing feasibility through standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances oscillation tolerance, avalanche tolerance, and maximum controllable current density by gradually distributing carrier concentration, preventing snap-off and radiofrequency oscillation, while maintaining withstand voltage and reducing total loss.
Implementation Method 1
a gradient of carrier concentration at a connection between the n-type drift layer and the n-type buffer layer is 20 to 2000 cm−4
Data Source
AI summary
A p-type anode layer (2) is provided on an upper surface of an n-type drift layer (1). An n-type cathode layer (3) is provided on a lower surface of the n−-type drift layer (1). An n-type buffer layer (4) is provided between the n−-type drift layer (1) and the n-type cathode layer (3). A peak impurity concentration in the n-type buffer layer (4) is higher than that in the n−-type drift layer (1) and lower than that in the n-type cathode layer (3). A gradient of carrier concentration at a connection between the n−-type drift layer (1) and the n-type buffer layer (4) is 20 to 2000 cm−4.