Semiconductor Device Buffer Layers Prevent Photoresist Poisoning

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Solution Overview

Problem

The existing semiconductor manufacturing processes using copper for metal wiring face challenges with photoresist poisoning and plasma damage during etching and ashing, leading to distorted metal wiring shapes and potential gate insulating layer damage, which affects the reliability and performance of semiconductor devices.

Innovation Solution

A dual damascene process is implemented with the use of buffer layers and a hard mask made of nitride-based materials to prevent photoresist poisoning and plasma damage, ensuring precise etching and filling of trenches and via holes without distorting the metal wiring shape or damaging the gate insulating layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dual damascene process is used with copper wiring, then low resistivity and high reliability are achieved, but photoresist poisoning and plasma damage occur during etching and ashing

Engineering Contradiction:
Improvewiring reliabilityVSAvoidphotoresist poisoning and plasma damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A nitrogen-containing protective film is introduced as an intermediary layer between the photoresist and the underlying structures. This protective film acts as a mediator that prevents direct harmful interactions: it stops photoresist components from penetrating and poisoning the low-k dielectric during ashing, and shields the gate insulating layer from plasma damage during etching operations. The protective film thus resolves the contradiction by enabling the dual damascene process to proceed without the harmful side effects.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If high intensity plasma is used during etching and ashing, then precise patterning is achieved, but gate insulating layer damage occurs

Engineering Contradiction:
Improvepatterning precisionVSAvoidgate insulating layer damage
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The nitrogen-containing protective film is formed beforehand on the gate insulating layer and other sensitive structures before the plasma etching and ashing processes. This pre-formed protective layer serves as a cushion that absorbs and dissipates the harmful effects of high-intensity plasma, preventing direct damage to the gate insulating layer while still allowing precise patterning to be achieved through the photoresist and etch mask systems.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Manufacturing precision

If photoresist layer is used as etch mask, then trench and via hole patterning is achieved, but photoresist poisoning causes residual parts and distorted metal wiring shape

Engineering Contradiction:
Improvetrench and via hole patterningVSAvoidmetal wiring shape
Core Design Contradiction:
Manufacturing precisionVSShape

Solution Approach 1:

The nitrogen-containing protective film serves as an intermediary barrier that prevents photoresist components from migrating into and contaminating the low-k dielectric material during the ashing process. By blocking this harmful interaction, the protective film prevents the formation of residual parts and maintains the intended shape of metal wirings, thus resolving the contradiction between achieving precise patterning and maintaining proper metal wiring geometry.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents photoresist layer poisoning and plasma damage, reducing resistance in metal wiring, enhancing the reliability and yield of semiconductor devices by maintaining the integrity of the gate insulating layer and preventing peeling between layers.

Implementation Method 1

a reaction between the second interlayer dielectric 50 and the first photoresist layer 60 causes photoresist poisoning

Methodology Applied
Scientific EffectPhotoresist poisoning:

Implementation Method 2

An ashing process, using plasma generated by RF or microwaves, removes the photoresist material forming the via hole pattern

Methodology Applied
Scientific EffectPlasma: Plasma

Implementation Method 3

An ashing process, using plasma generated by RF or microwaves

Methodology Applied
Scientific EffectRF heating:

Implementation Method 4

When high intensity plasma is used, a strong electric field between the gate and substrate of the semiconductor device can cause plasma damage to the gate insulating layer

Methodology Applied
Scientific EffectPlasma damage: Plasma

Data Source

PatentUS7572728B2Semiconductor device and method for manufacturing the same
Publication Date: 2009.08.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US7572728B2 patent drawing
  • US7572728B2 patent drawing
  • US7572728B2 patent drawing

AI summary

A semiconductor device and method with a dual damascene pattern uses buffer layers to prevent photoresist layer poisoning due to a reaction between an interlayer dielectric and a photoresist layer. Embodiments also relate to reducing the effects of plasma damage occurring during an etching or ashing process.