Semiconductor Device with Buffer Layers for Strain Management
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Solution Overview
Problem
The fabrication of horizontal gate-all-around (HGAA) transistors is challenging due to insufficient etch selectivity and strain caused by lattice mismatch in silicon (Si) and silicon germanium (SiGe) layers, leading to nanowire loss and imperfections.
Innovation Solution
A stack with layers having a lattice constant equal to or substantially equal to Si, SiGe, or germanium is used, including materials like ZnS1-xSex, Al1-xGaxP, GaP1-xAsx, and MgS1-xSex, which allows for high selectivity in etching and reduces strain, enabling the formation of nanowires without damage and minimizing the transition layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon (Si) and silicon germanium (SiGe) layers are used in the stack, then the fabrication process is simplified and compatibility with conventional CMOS processes is maintained, but lattice mismatch causes strain and insufficient etch selectivity leading to nanowire loss
Solution Approach 1:
The patent introduces buffer layers composed of materials with lattice constants intermediate between SiGe and the nanowire material (Si, Ge, or SiC). These buffer layers act as intermediaries that gradually transition the lattice constant, reducing strain and preventing dislocation while maintaining etch selectivity. The buffer layers are disposed between the SiGe layer and the nanowire layer, creating a gradual lattice constant transition that resolves the contradiction between manufacturing simplicity and nanowire formation quality.
2Reliability
If the lattice constant difference between layers is increased to improve etch selectivity, then nanowire loss is reduced, but strain and lattice mismatch limitations increase
Solution Approach 1:
The patent segments the transition from SiGe to nanowire material into multiple intermediate steps using buffer layers with progressively changing lattice constants. Instead of a single large lattice constant difference, the transition is divided into smaller steps across multiple buffer layers, each with a manageable lattice constant difference. This segmentation maintains etch selectivity while reducing strain and preventing dislocation accumulation.
Solution Approach 2:
The patent systematically changes the lattice constant parameter across the stack by introducing buffer layers with intermediate lattice constants. The lattice constant is gradually increased from the SiGe layer through multiple buffer layers with progressively higher lattice constants, eventually reaching the nanowire layer. This parameter change approach maintains a reasonable lattice constant difference for etch selectivity while avoiding excessive strain through the gradual transition.
3Object-affected harmful factors
If a transition layer is formed between Si/SiGe layers to reduce strain, then lattice mismatch is partially addressed, but the transition layer increases device complexity and may not fully prevent nanowire damage
Solution Approach 1:
The patent uses buffer layers as intermediaries between SiGe and nanowire layers, with each buffer layer having a lattice constant intermediate between its neighbors. This intermediary approach provides gradual strain relief through multiple small transitions rather than a single large transition, achieving better strain management with controlled complexity. The buffer layers are specifically designed with lattice constants that facilitate both strain reduction and etch selectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of nanowires without strain and lattice mismatch limitations, increasing etch selectivity and reducing nanowire loss, thereby simplifying the fabrication process and improving the quality of HGAA transistors.
Implementation Method 1
A second etching process is performed on a first portion of each of the first epitaxial layers in the channel region of the fin using a hydrocarbon etch chemistry. The second etching process etches the first epitaxial layers at a higher etch rate than the second etching process etches the second epitaxial layers.
Implementation Method 2
A stack including plural first epitaxial layers and plural second epitaxial layers alternatingly stacked over each other is formed on a substrate
Data Source
AI summary
A stack is formed on a substrate. The stack includes plural first epitaxial layers and plural second epitaxial layers alternatingly stacked over each other. The first epitaxial layers include sulfur, phosphorous, selenium, arsenic, or combinations thereof. A first etching process is performed on the stack to form a fin. A dielectric layer is formed over the fin. A channel region of the fin is exposed. A second etching process is performed on a first portion of each of the first epitaxial layers in the channel region of the fin using a hydrocarbon etch chemistry. The second etching process etches the first epitaxial layers at a higher etch rate than the second etching process etches the second epitaxial layers. A gate structure is formed around a first portion of each of the second epitaxial layers in the channel region of the fin.