Semiconductor Buffer Management via Dedicated Channels
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Solution Overview
Problem
Semiconductor devices face inefficiencies in operation speed due to the need for arbitration in direct memory access units when multiple units access the main memory simultaneously, leading to increased load on the central processing unit and reduced data transfer efficiency.
Innovation Solution
A semiconductor device with a buffer management unit that allows function blocks to access a buffer memory through dedicated channels, reducing the load on the data bus and control bus by managing storage space and validity of data, enabling efficient write and read operations through direct memory access units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple direct memory access units simultaneously access the main memory, then data transfer efficiency is improved, but arbitration complexity and CPU load increase
Solution Approach 1:
The patent divides the memory access system into separate read and write channels. The read channel handles read requests from multiple function blocks, while the write channel handles write requests. This segmentation eliminates the need for complex arbitration between multiple simultaneous access units, as each channel operates independently for its specific access type.
Solution Approach 2:
The patent introduces a buffer management unit as an intermediary between the function blocks and the main memory. This unit manages the buffer memory and coordinates access requests, acting as a mediator that simplifies the access control mechanism and reduces the burden on the CPU for arbitration decisions.
2Speed
If direct memory access units simultaneously access the main memory, then data transfer speed is improved, but CPU load increases
Solution Approach 1:
By segmenting access into separate read and write channels, the system enables simultaneous data transfer operations without requiring CPU intervention for arbitration. The CPU only needs to manage the buffer memory through the buffer management unit, significantly reducing its load while maintaining high data transfer speeds.
Solution Approach 2:
The buffer management unit autonomously manages buffer memory allocation and access coordination without requiring continuous CPU involvement. This self-service capability allows the system to maintain fast data transfer speeds while minimizing CPU resource consumption.
3Productivity
If a buffer management unit is introduced to manage storage space, then access efficiency is improved, but device complexity increases
Solution Approach 1:
The buffer management unit serves as an intermediary layer between function blocks and main memory, managing buffer allocation and access rights. While this adds a management component, it simplifies the overall system architecture by providing a centralized coordination mechanism that improves access efficiency without requiring complex distributed arbitration protocols.
Data Source
AI summary
A semiconductor device includes a buffer memory, a plurality of function blocks, each of which transmits to a request of access to the buffer memory, and accesses the buffer memory according to a response to the request of access; and a buffer management unit suitable for receiving the request of access, and transmitting the response to the request of access according to a status of the buffer memory, wherein the buffer management unit and each of the plurality of function blocks may communicate through a dedicated channel.