Semiconductor Bulk Bias Control for Leakage Current Reduction
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Solution Overview
Problem
Semiconductor integrated circuit devices face significant leakage current issues due to abnormal bulk voltage reversal during power-up periods, particularly in PMOS transistors, where external voltages may be abnormally input, leading to increased power consumption and reduced device efficiency.
Innovation Solution
A semiconductor integrated circuit device is configured with PMOS and NMOS bulk bias generation blocks that output specific external voltages as bulk voltages during power-up and power-down modes, using control signals and switching units to manage voltage levels and prevent leakage current, ensuring the bulk voltage remains stable and higher than the source voltage in power-down mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a boosting voltage VPP_EXT higher than external voltage VDD is applied as bulk bias in PMOS transistor, then leakage current is reduced in power-down mode, but abnormal bulk voltage is applied during power-up period causing bulk voltage reversal and increased leakage current
Solution Approach 1:
The bulk bias voltage is made dynamic by switching between different voltage levels based on operational mode. During power-up period, the bulk bias is set to external voltage VDD level, while in power-down mode it switches to boosting voltage VPP_EXT level. This dynamic adjustment prevents bulk voltage reversal during power-up while maintaining low leakage current during power-down operation.
Solution Approach 2:
The bulk bias voltage parameter is changed according to the operational state of the device. By detecting the power-up/power-down state and adjusting the bulk bias voltage accordingly, the system optimizes both reliability during transitions and energy efficiency during steady-state operation.
2Speed
If threshold voltage is reduced to achieve improved transition speed with low voltage level, then device speed is improved, but sub-threshold leakage increases
Solution Approach 1:
The bulk bias control mechanism proactively prevents sub-threshold leakage by maintaining proper bulk-to-source voltage relationships before leakage can occur. By ensuring bulk voltage is appropriately controlled during power-up and power-down transitions, the system counteracts the inherent leakage problem caused by low threshold voltage design.
Data Source
AI summary
A semiconductor integrated circuit device having a bulk bias control function is provided. The semiconductor integrated circuit device may be configured to output the first external voltage as a bulk voltage of a transistor in a power-up period, and to output a second external voltage having a higher level than the first external voltage as the bulk voltage of the transistor in a power-down mode.