Semiconductor Device Bulk Pattern Electron Hole Supply
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Solution Overview
Problem
The challenge lies in manufacturing three-dimensional nonvolatile memory devices where memory cells are vertically stacked, requiring efficient electron hole supply and connection structures to enhance reliability and integration density.
Innovation Solution
A semiconductor device structure and manufacturing method involving an insulating layer with a bulk pattern containing an electron hole source, a stack structure with alternately stacked conductive and insulating layers, and a channel pattern penetrating the stack structure, connected by a connecting layer to facilitate electron hole supply and uniform memory cell characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are vertically stacked to increase integration density, then device capacity increases, but manufacturing complexity and connection reliability become problematic
Solution Approach 1:
The device is segmented into distinct functional regions: bulk patterns embedded in the insulating layer, vertically stacked memory cells with alternating conductive and insulating layers, and channel patterns penetrating through the stack. This segmentation allows independent optimization of each component while maintaining overall integration density.
Solution Approach 2:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked cells. Multiple memory cells are arranged in the vertical dimension, increasing storage capacity without expanding the planar footprint, thus achieving higher integration density through dimensional transformation.
2Reliability
If complex connection structures are added to supply electron holes in three-dimensional devices, then erase operation efficiency improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The bulk patterns serve multiple functions: they are embedded in the insulating layer to provide electrical connection, act as electron hole sources for erase operations, and maintain structural integrity of the vertically stacked cells. This multi-functionality eliminates the need for separate connection structures, reducing overall device complexity.
Solution Approach 2:
The channel patterns automatically penetrate through the stacked memory cells and connect to the bulk patterns, establishing electron hole supply paths without requiring additional connection structures. The vertical stacking geometry itself facilitates the connection, making the system self-organizing and reducing manufacturing complexity.
3Reliability
If uniform electron hole supply is achieved across all memory cells, then erase operation reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
Each bulk pattern is locally embedded in the insulating layer at specific positions corresponding to groups of memory cells. The bulk patterns are strategically positioned to ensure uniform electron hole distribution across all vertically stacked cells, with each bulk pattern serving its local region while maintaining overall uniformity through consistent geometric arrangement.
Data Source
AI summary
A semiconductor device may include an insulating layer, a bulk pattern, a stack structure, and a channel pattern. A first trench may be formed in the insulating layer. A bulk pattern may be located in the first trench and includes a metal pattern and an electron hole source. The stack structure may be located on the insulating layer and includes conductive layers and insulating layers, which are alternately stacked. The channel pattern may penetrate the stack structure, and may be supplied with electron holes from the bulk pattern.