Semiconductor Package Conductive Bump Area Ratio for Thermal Management

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Solution Overview

Problem

The increasing number of input/output connections in multi-functional semiconductor chip packages leads to thermal electrical problems such as heat dissipation, cross talk, and electromagnetic interference, affecting the reliability and quality of products.

Innovation Solution

A semiconductor package design featuring conductive bumps with different areas in the central and peripheral regions, where the area ratio of the larger bumps to smaller bumps is greater than 1 and less than or equal to 3, enhancing thermal conductivity and reducing electrical resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of input/output connections is increased to support multi-functional chips, then the functionality and connectivity of the semiconductor package is improved, but thermal electrical problems such as heat dissipation, cross talk, and electromagnetic interference worsen

Engineering Contradiction:
ImprovefunctionalityVSAvoidthermal electrical problems
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by differentiating the areas of conductive bumps based on their location. Central bumps have a first area while peripheral bumps have a second area, with the area ratio controlled between 1 and 3. This local differentiation optimizes thermal and electrical properties in different regions of the package, addressing heat dissipation and electromagnetic interference issues that arise from increased I/O connections.

Inventive Principle:
Principle #3Local quality

2Temperature

If the area of conductive bumps is increased to improve thermal conductivity, then heat dissipation is improved, but the space available for other connections is reduced

Engineering Contradiction:
Improvethermal conductivityVSAvoidavailable space
Core Design Contradiction:
TemperatureVSArea of stationary object

Solution Approach 1:

The patent applies parameter changes by controlling the area ratio parameter between central and peripheral conductive bumps to be between 1 and 3. This parameter optimization ensures sufficient thermal conductivity through larger central bumps while maintaining adequate space for peripheral connections, resolving the trade-off between heat dissipation and available connection space.

Inventive Principle:
Principle #35Parameter changes

3Temperature

If the area ratio of central conductive bump to peripheral conductive bump is increased to improve thermal properties, then heat dissipation is improved, but electrical resistance may increase

Engineering Contradiction:
Improveheat dissipationVSAvoidelectrical resistance
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent applies parameter changes by establishing an optimized range for the area ratio parameter (between 1 and 3) of central to peripheral conductive bumps. This controlled parameter change balances thermal conductivity improvement with electrical resistance management, ensuring both heat dissipation and electrical performance requirements are met simultaneously.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves thermal and electrical properties by increasing thermal conductivity and reducing electrical resistance, thereby addressing the thermal electrical challenges associated with high I/O connections.

Implementation Method 1

A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area, wherein an area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

This design improves thermal and electrical properties by increasing thermal conductivity and reducing electrical resistance, thereby addressing the thermal electrical challenges associated with high I/O connections.

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS10109608B2Semiconductor package
Publication Date: 2018.10.23 MEDIATEK INC
  • US10109608B2 patent drawing
  • US10109608B2 patent drawing
  • US10109608B2 patent drawing

AI summary

The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.