Semiconductor Package Bump Structure for Warpage and Cold Joints
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Solution Overview
Problem
Semiconductor packages often experience warpage issues during bonding, leading to bridging or cold joint problems, particularly in large chip-on-wafer (CoW) packages, due to complex material constitutions, which affect the reliability of the package structure.
Innovation Solution
The design of bump structures on semiconductor packages is adjusted to mitigate warpage by varying their heights and widths, with first bump structures having a smaller height and greater width in the center region and second bump structures having a greater height and smaller width in the side regions, compensating for warpage and preventing cold joints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform bump structures are used on semiconductor packages, then manufacturing is simple, but warpage and cold joint problems occur during bonding
Solution Approach 1:
The patent applies local quality by varying the bump structure dimensions (height and width) based on their location on the semiconductor package. Center region bumps have different dimensions than side region bumps, allowing each region to be optimized for its specific warpage characteristics while maintaining manufacturing feasibility through a systematic gradient approach.
Solution Approach 2:
The patent changes physical parameters of the bump structures, specifically height and width, to compensate for warpage. By adjusting these parameters across different regions (center vs. side), the bonding surface is optimized to maintain contact and prevent cold joints during the bonding process.
2Reliability
If bump structures are designed to compensate for warpage, then bonding reliability improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the semiconductor package surface into distinct regions (center region and side regions) and applies different bump structure designs to each segment. This segmentation allows targeted warpage compensation in each region while maintaining overall manufacturing efficiency through a modular approach.
Solution Approach 2:
The patent introduces asymmetry in bump structure dimensions between different regions of the semiconductor package. The non-uniform bump design (different heights and widths in center vs. side regions) creates an asymmetric structure that specifically addresses the asymmetric warpage patterns typical in large CoW packages.
Data Source
AI summary
A package structure includes a circuit substrate, a semiconductor package, first bump structures and second bump structures. The semiconductor package is disposed on the circuit substrate, wherein the semiconductor package includes a center region and side regions surrounding the center region. The first bump structures are disposed on the center region of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate. The second bump structures are disposed on the side regions of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate, wherein the first bump structures and the second bump structures have different heights and different shapes.