Semiconductor Bump Electrode Design for Chip Size Reduction

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Solution Overview

Problem

The miniaturization of semiconductor chips has led to a situation where the electrode pad occupies a large portion of the chip footprint, making it difficult to reduce the size of the bump electrode while ensuring sufficient contact area and maintaining the flatness of the passivation film, which increases manufacturing costs and complexity.

Innovation Solution

The semiconductor device features a passivation film with an opening, allowing the bump electrode to be formed larger than the electrode pad, with internal wirings arranged under the bump electrode to reduce chip size and maintain passivation film flatness, preventing gaps and improving connection reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the electrode pad is made larger to ensure sufficient contact area with the bump electrode, then the contact reliability is improved, but the chip footprint increases and manufacturing cost increases

Engineering Contradiction:
Improvecontact reliabilityVSAvoidchip footprint
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extends the electrode pad in the vertical direction by forming it on an extended region of the substrate that protrudes from the chip surface. This allows the electrode pad to have a larger area without increasing the chip footprint, as the extended portion is located outside the chip boundaries. The electrode pad can thus provide sufficient contact area with the bump electrode while the chip itself maintains a compact size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If the bump electrode is made smaller to reduce chip size, then the device miniaturization is improved, but the contact area with the inner lead becomes insufficient

Engineering Contradiction:
Improvedevice sizeVSAvoidcontact area
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent compensates for the reduced bump electrode size by extending the electrode pad onto an extended region of the substrate. This extension provides additional contact area between the electrode pad and the inner lead, ensuring sufficient bonding area even when the bump electrode itself is miniaturized. The extended region acts as a contact area enhancement zone that decouples the bump electrode size from the required contact area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Stability of the object's composition

If the electrode pad is made larger to maintain passivation film flatness, then the flatness is improved, but the manufacturing complexity increases

Engineering Contradiction:
Improvepassivation film flatnessVSAvoidmanufacturing complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent maintains passivation film flatness by forming the electrode pad on an extended region of the substrate that is located outside the chip area. This separation allows the passivation film on the chip surface to remain flat and simple, while the electrode pad extends outward to provide the necessary structural support and contact area. The extended region acts as a dedicated zone for electrode pad formation without complicating the chip's internal structure or passivation process.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for a reduction in semiconductor device size without increasing manufacturing complexity or cost, while enhancing the flatness of the passivation film and reducing the risk of short circuits by utilizing the area under the bump electrode effectively.

Implementation Method 1

the bump electrode thereof is bonded to the inner lead on the film carrier using a technology such as a thermal compression bonding process

Methodology Applied
Scientific EffectThermal compression bonding:

Data Source

PatentUS9196580B2Semiconductor device and semiconductor package containing the same
Publication Date: 2015.11.24 LAPIS SEMICON CO LTD
  • US9196580B2 patent drawing
  • US9196580B2 patent drawing
  • US9196580B2 patent drawing

AI summary

A semiconductor device, having an electrode pad as a part of wirings on the uppermost layer thereof, includes a passivation film and a bump electrode for external connection. The passivation film is formed on the electrode pad, and the bump electrode is formed on the passivation film and electrically connected to the electrode pad. The electrode pad is formed so as to be smaller in size than the bump electrode, and parts of the wiring on the uppermost layer are formed under the bump electrode. In this manner, it is possible to utilize the area under the bump electrode effectively without sacrificing flatness of the passivation film. As a result, the semiconductor device and the semiconductor package can be made smaller.