Semiconductor Interconnection Structure Without Bumps for Dense 3D Stacks
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Solution Overview
Problem
The challenge is to increase the density and reliability of interconnections between semiconductor chip stacks and chips, as existing organic material-based insulating layers lead to increased leakage current and contact resistance due to narrowed interconnection pitch and the use of bumps, which reduces the reliability of connections.
Innovation Solution
A method involving a semiconductor device with inorganic insulating layers and vertical and horizontal interconnections that directly connect semiconductor chip stacks and chips, eliminating the need for bumps and reducing resistance by using a substrate with adhesive layers and inorganic materials like SiO2, SiON, and Si3N4, allowing for higher integration density and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If organic material-based insulating layers are used in interconnections, then ease of manufacture is improved, but leakage current increases when interconnection pitch is narrowed
Solution Approach 1:
The patent changes the material parameter of the insulating layer from organic material to inorganic material (such as silicon oxide, silicon nitride). This material substitution fundamentally alters the electrical properties, providing superior insulation performance and preventing leakage current even when interconnection pitch is narrowed, while still being compatible with standard semiconductor manufacturing processes.
2Ease of manufacture
If bumps are used for connecting semiconductor chip stack and semiconductor chip to interposer, then ease of manufacture is improved, but contact resistance and resistance of bump itself increase
Solution Approach 1:
The patent extracts and eliminates the bump component from the interconnection structure. By removing the bump and its associated insulating layer, the invention creates a direct wire-like connection between the semiconductor chip stack and the interposer. This eliminates the contact resistance and resistance of the bump itself, significantly reducing overall interconnection resistance while maintaining manufacturability through direct patterning processes.
3Ease of manufacture
If bumps are used for connecting semiconductor chip stack and semiconductor chip to interposer, then ease of manufacture is improved, but reliability of interconnection is reduced
Solution Approach 1:
The patent extracts and eliminates the bump component from the interconnection structure. By removing the bump and its associated insulating layer, the invention creates a direct wire-like connection between the semiconductor chip stack and the interposer. This eliminates the contact resistance and resistance of the bump itself, significantly reducing overall interconnection resistance while maintaining manufacturability through direct patterning processes.
4Productivity
If interconnection pitch is narrowed to increase density, then productivity is improved, but leakage current increases when organic insulating layer is used
Solution Approach 1:
The patent changes the material parameter of the insulating layer from organic material to inorganic material (such as silicon oxide, silicon nitride). This material substitution fundamentally alters the electrical properties, providing superior insulation performance and preventing leakage current even when interconnection pitch is narrowed, while still being compatible with standard semiconductor manufacturing processes.
Data Source
AI summary
A first substrate having a first face and a second face is prepared. The first face has a plurality of product regions defined thereon. An electrode pad forming side of each of a semiconductor chip stack and a semiconductor chip is attached to each corresponding product region of the plurality of product regions. The second face of the first substrate is thinned. A first inorganic insulating layer is formed on the second face. A first vertical interconnection penetrates the first inorganic insulating layer and the first substrate and is electrically connected to an electrode pad of the semiconductor chip stack. A second vertical interconnection penetrates the first inorganic insulating layer and the first substrate and is electrically connected to an electrode pad of the semiconductor chip. A first horizontal interconnection electrically connects a part of the first vertical interconnection to a part of the second vertical interconnection.