Semiconductor Package Bump Grinding Depth Control
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Solution Overview
Problem
The chip-first type semiconductor package fabrication method faces challenges in controlling the grinding depth of the encapsulation, leading to either shallow or over-grinding, which affects the exposure and integrity of metal bumps and the chip's sidewalls.
Innovation Solution
The method involves forming first and second bumps with distinct layers on the chip's surface, where the second bumps are step-shaped and used to determine the proper grinding depth, ensuring all first bumps are exposed and the chip's sidewalls are encapsulated, preventing cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the encapsulation is ground to expose metal bumps, then the metal bumps can be accessed for electrical connection, but the grinding depth is difficult to control resulting in either shallow grinding (bumps not fully exposed) or over-grinding (bumps disappear)
Solution Approach 1:
The patent applies preliminary action by forming a protective layer over the metal bumps before encapsulation. This protective layer serves as a predetermined depth reference that prevents over-grinding during the encapsulation removal process. The grinding operation is designed to expose the protective layer while preserving the metal bumps underneath, thus ensuring controlled grinding depth and maintaining bump integrity.
Solution Approach 2:
The protective layer acts as an intermediary element between the grinding tool and the metal bumps. By grinding through the encapsulation to expose the protective layer (而非 directly exposing the metal bumps), the patent creates a buffer zone that prevents direct contact between the grinding process and the vulnerable metal bumps, thereby avoiding over-grinding damage.
2Manufacturing precision
If the encapsulation is ground deeply to expose all metal bumps, then all bumps can be accessed, but the chip sidewalls become exposed and vulnerable to cracking during package picking
Solution Approach 1:
The patent applies preliminary action by forming a protective layer that extends over the chip sidewalls before encapsulation. During the grinding process, this protective layer remains as a reference indicator, allowing the encapsulation to be removed to a controlled depth that exposes the bumps while preserving the protective layer coverage on the sidewalls, thus preventing crack propagation.
Solution Approach 2:
The protective layer serves as a beforehand cushioning mechanism for the chip sidewalls. By maintaining the protective layer coverage on the sidewalls after grinding (while exposing the metal bumps through the encapsulation), the patent provides a protective buffer that prevents crack initiation and propagation during subsequent package handling and picking operations.
3Ease of operation
If the metal bumps are fully exposed from the encapsulation, then electrical connection can be established, but the grinding process becomes difficult to control and may remove too much material
Solution Approach 1:
The protective layer serves as an intermediary grinding stop indicator. The grinding process is designed to remove encapsulation material until the protective layer becomes visible at the surface, at which point grinding is stopped. This intermediary reference layer provides a clear visual cue that ensures consistent grinding depth across all packages, making the process easy to control while maintaining precision.
Solution Approach 2:
The protective layer performs a self-service function by automatically serving as its own depth reference indicator. The grinding process inherently uses the exposure of the protective layer as the stopping criterion, eliminating the need for external measurement or control mechanisms. The system self-regulates the grinding depth through the visual exposure of the protective layer.
Data Source
AI summary
A semiconductor package comprising plurality of bumps and fabricating method thereof. The package has a chip, a plurality of first and second bumps, an encapsulation, a redistribution. The chip has a plurality of pads and an active area and the active surface has a first area and a second area surrounding the first, the pads formed on a first area of the active surface, each first bump formed on the corresponding pad. The second bumps are formed on the second area, each second bump has first and second different width layers. The encapsulation encapsulates the chip and bumps and is ground to expose the bumps therefrom. During grinding, all of the first bumps are completely exposed by determining a width of an exposed surface of the second bump to electrically connect to the redistribution is increased. Therefore, a shallow-grinding or over-grinding does not occur.