Semiconductor Device Bump Height Compensation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In laminated solid-state imaging devices, connection defects occur due to height variations in bump electrodes formed by electroless plating, leading to defective pixels, as the peripheral area bumps may not connect properly with the second substrate, resulting in inconsistent microstructure formation and reduced efficiency.

Innovation Solution

The semiconductor device design includes strategically varying the height and diameter of base electrodes and bumps between different areas on the substrates, with the second base electrode being taller than the first, and the second bump being smaller in diameter, ensuring consistent contact and reducing connection defects by adjusting the load distribution during bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If electroless plating is used to form bump electrodes, then microstructure formation is suitable and seed layer can be patterned before plating, but height variation of bump electrodes within wafer surface is large especially in peripheral area

Engineering Contradiction:
Improvemicrostructure formation suitabilityVSAvoidbump electrode height uniformity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent divides the wafer surface into different regions (central area and peripheral area) and applies different base electrode height configurations for each region. The peripheral area base electrodes are made taller than central area base electrodes to compensate for the height variation inherent in electroless plating, ensuring uniform bump electrode heights across the entire wafer surface.

Inventive Principle:
Principle #3Local quality

2Reliability

If bump electrodes in peripheral area are too short, then connection to second substrate cannot be established, but making them taller increases height difference from central area bumps

Engineering Contradiction:
Improveconnection reliabilityVSAvoidheight difference between central and peripheral bumps
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent implements region-specific base electrode height design where peripheral area base electrodes are taller than central area base electrodes. This local differentiation ensures that peripheral bumps achieve sufficient height for reliable connection while maintaining controlled height differences through systematic design.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the height parameter of base electrodes based on their location on the wafer surface. By adjusting the base electrode height parameter differently for central and peripheral regions, the patent optimizes both connection reliability and height uniformity of the final bump electrodes.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If varying base electrode heights are used to compensate peripheral area, then connection defects are reduced, but device structure becomes more complex

Engineering Contradiction:
Improveconnection defect reductionVSAvoidbase electrode structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality differentiation by configuring base electrodes with different heights in different regions. This approach reduces connection defects through targeted height compensation while maintaining a relatively simple overall structure that can be implemented through standard fabrication processes.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design reduces connection defects by ensuring proper contact between substrates, improving the reliability of pixel connections and overall device performance by minimizing height differences and optimizing load distribution during bonding.

Implementation Method 1

In the electroless plating, a metal structure is formed only on a metal surface that is exposed to a plating bath

Methodology Applied
Scientific EffectElectroless plating: Deposition (physical)

Data Source

PatentUS10056344B2Semiconductor device
Publication Date: 2018.08.21 OLYMPUS CORPORATION(JP)
  • US10056344B2 patent drawing
  • US10056344B2 patent drawing
  • US10056344B2 patent drawing

AI summary

A first surface of a first substrate included in a semiconductor device includes a first area in which a plurality of first connecting portions are disposed and a second area in which a plurality of second connecting portions are disposed. A second surface of a second substrate included in the semiconductor device includes a third area in which the plurality of first connecting portions are disposed and a fourth area in which the plurality of second connecting portions are disposed. The second area surrounds the first area on the first surface. The fourth area surrounds the third area on the second surface. A height of the second base electrode in a thickness direction of the first substrate is greater than a height of the first base electrode in the thickness direction.