Semiconductor Bump Interconnects with Encapsulant Redistribution Layers
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Solution Overview
Problem
The manufacturing of wafer-level chip-scale packages (WLCSPs) with top and bottom interconnect structures is hindered by the difficulty and cost of forming conductive through-hole vias, which are time-consuming and challenging due to increasing die size reductions and pin density, making it hard to mount dies on conventional motherboards configured for larger input/output bumps with a larger pitch.
Innovation Solution
A semiconductor device design featuring bumps partially enclosed by an encapsulant material with redistribution layers (RDLs) that connect contact pads to the bumps, eliminating the need for through-silicon vias and simplifying the mounting process by using solder bumps formed directly on a substrate, allowing for top and bottom surface interconnects without additional pad layers or insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conductive through-hole vias are formed within the WLCSP perimeter to create top and bottom interconnect structures, then the WLCSP can be mounted to motherboards and stacked packages can be formed, but the manufacturing process becomes difficult and time-consuming with increased cost
Solution Approach 1:
The patent extracts the interconnect function from the traditional through-hole via structure and relocates it to the encapsulant material. Instead of forming complex through-silicon vias, the invention uses conductive traces embedded within the encapsulant to achieve the same electrical interconnection between top and bottom surfaces, thereby simplifying manufacturing while maintaining mounting capability
Solution Approach 2:
The encapsulant material serves as an intermediary that performs dual functions: it provides mechanical encapsulation and protection while simultaneously serving as the medium for electrical interconnection through embedded conductive traces. This eliminates the need for separate via structures and simplifies the overall manufacturing process
2Productivity
If die size is reduced to achieve smaller semiconductor devices with higher pin density, then power consumption decreases and performance increases, but mounting on conventional motherboards becomes difficult
Solution Approach 1:
The patent transitions from planar interconnect arrangements to a three-dimensional encapsulated structure with top and bottom surfaces. By embedding conductive traces within the encapsulant volume and providing interconnects on both surfaces, the invention enables high-pin-count small dies to be mounted on conventional motherboards through stacked package configurations, effectively adding a vertical dimension to the interconnect architecture
Data Source
AI summary
A semiconductor device includes a semiconductor die having contact pads disposed over a surface of the semiconductor die, a die attach adhesive layer disposed under the semiconductor die, and an encapsulant material disposed around and over the semiconductor die. The semiconductor device further includes bumps disposed in the encapsulant material around a perimeter of the semiconductor die. The bumps are partially enclosed by the encapsulant material. The semiconductor device further comprises first vias disposed in the encapsulant. The first vias expose surfaces of the contact pads. The semiconductor device further includes a first redistribution layer (RDL) disposed over the encapsulant and in the first vias, and a second RDL disposed under the encapsulant material and the die attach adhesive layer. The first RDL electrically connects each contact pad of the semiconductor die to one of the bumps, and the second RDL is electrically connected to one of the bumps.