Semiconductor Bump Layout for Fine-Pitch Packaging Reliability
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Solution Overview
Problem
In the semiconductor industry, fine-pitch chip-on-film packages face issues such as metal bump overflow and misalignment during the reflow process, leading to circuit shortages and reduced bonding ability, while also struggling to reduce chip thickness.
Innovation Solution
The semiconductor device features a configuration of first and second bumps on the chip's active surface, with the second bumps closer to the fan-out region, allowing traces to pass through them to avoid misalignment and overflow, and a carrier on the chip's back surface to support thinning without cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If metal bumps are arranged in fine pitch on the chip, then the size and integration are improved, but metal bump overflow occurs during reflow process causing circuit shortage
Solution Approach 1:
The patent divides the chip surface into different regions with different bump pitch specifications. The first region has a first pitch suitable for fine-pitch packaging, while the second region has a second pitch (larger than the first pitch) that prevents metal bump overflow during reflow. This segmentation allows the chip to achieve fine-pitch integration in critical areas while maintaining manufacturing reliability in other areas.
Solution Approach 2:
Different regions of the chip are assigned different bump pitch characteristics based on their functional requirements. The first region uses smaller pitch for high integration, while the second region uses larger pitch for manufacturing stability. This local differentiation resolves the contradiction between fine-pitch requirements and overflow prevention.
2Manufacturing precision
If metal bumps are arranged in fine pitch on the chip, then the integration density is improved, but misalignment or alignment shifting occurs during application deteriorating bonding ability
Solution Approach 1:
The chip surface is segmented into regions with different pitch characteristics. The first region maintains fine pitch for high density, while the second region uses coarser pitch that is more tolerant to alignment variations, thereby preventing misalignment issues while preserving bonding ability.
Solution Approach 2:
Different local regions have different pitch qualities matched to their functional needs. The first region requires high precision fine pitch, while the second region uses a more robust larger pitch that accommodates alignment variations, resolving the contradiction between precision and bonding reliability.
3Length of moving object
If the chip thickness is reduced to meet fine-pitch package requirements, then the package size is improved, but the chip becomes more fragile and difficult to manufacture
Solution Approach 1:
A carrier is attached to the back surface of the chip before the thinning process. This preliminary action provides mechanical support during manufacturing operations, enabling the chip to be thinned to the required small thickness without becoming too fragile to handle or process, thus resolving the contradiction between reduced thickness and manufacturing ease.
Data Source
AI summary
A semiconductor device includes a chip, a plurality of first bumps, and a plurality of second bumps. The chip includes an active surface. The first bumps are disposed on the active surface along a first direction. The second bumps are disposed on the active surface along a second direction parallel to the first direction, wherein one of the second bumps is located between adjacent two of the first bumps, a closest distance from the second bumps to the fan-out region is smaller than a closest distance from the first bumps to the fan-out region, and a first width of one of the first bumps is larger than a second width of one of the second bumps.