Semiconductor Bump Locking via Substrate Cavities
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Solution Overview
Problem
Semiconductor devices face issues with electrical interconnects detaching or delaminating under thermal or mechanical stress, limiting the robustness of the bond between the semiconductor device and the substrate.
Innovation Solution
A semiconductor device with a substrate and a conductive layer featuring cavities formed through openings in the layer, where the bump material extends into these cavities to create a robust bond, utilizing an etch-resistant conductive layer for enhanced mechanical and thermal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bump interconnect is used to connect semiconductor device to substrate, then electrical connection is achieved, but the bond detaches or delaminates under thermal or mechanical stress
Solution Approach 1:
The invention transitions from a two-dimensional surface bond to a three-dimensional anchored bond by forming cavities in the substrate and extending bump material into these cavities. This dimensional change creates a mechanical interlock that prevents delamination under thermal and mechanical stress, directly resolving the contradiction between achieving electrical connection and maintaining bond strength.
Solution Approach 2:
The bump material is nested within the cavities formed in the substrate, creating a hierarchical structure where the interconnect is embedded within the substrate rather than merely surface-mounted. This nesting provides mechanical anchoring that enhances reliability under stress while maintaining electrical connectivity.
2Ease of manufacture
If mechanical bond is formed by pressing bumps into vias or holes, then connection is created, but bond strength is limited to shear strength between surfaces
Solution Approach 1:
The invention changes the geometric parameters of the interconnect structure by forming cavities with widths greater than the opening sizes in the conductive layer. This parameter change allows the bump material to extend beyond the opening boundaries into the cavities, creating a mechanically interlocked structure that exceeds simple shear strength limitations while maintaining ease of manufacture through standard etching and deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a robust electrical interconnect bond that is resistant to thermal and mechanical stress, reducing the risk of delamination and improving the reliability of semiconductor devices by locking the bump material within wider cavities, ensuring a strong and stable connection.
Implementation Method 1
an etch-resistant conductive layer for enhanced mechanical and thermal stability
Implementation Method 2
A bump material bonds the semiconductor die to the first conductive layer by extending the bump material into the cavities
Implementation Method 3
The solution provides a robust electrical interconnect bond that is resistant to thermal and mechanical stress, reducing the risk of delamination and improving the reliability of semiconductor devices by locking the bump material within wider cavities
Data Source
AI summary
A semiconductor device has a base substrate with first and second etch-resistant conductive layers formed over opposing surfaces of the base substrate. First cavities are etched in the base substrate through an opening in the first conductive layer. The first cavities have a width greater than a width of the opening in the first conductive layer. Second cavities are etched in the base substrate between portions of the first or second conductive layer. A semiconductor die is mounted over the base substrate with bumps disposed over the first conductive layer. The bumps are reflowed to electrically connect to the first conductive layer and cause bump material to flow into the first cavities. An encapsulant is deposited over the die and base substrate. A portion of the base substrate is removed down to the second cavities to form electrically isolated base leads between the first and second conductive layers.