Semiconductor Package Bump Formation for Uniform Multi-Height Plating
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Solution Overview
Problem
Existing semiconductor packaging methods struggle with controlling different bump heights and sizes on a wafer, leading to non-uniformity and reduced manufacturing yield due to faster plating of larger bumps, which affects chip performance and yield.
Innovation Solution
A method involving the formation of a seed layer over semiconductor devices with patterned passivation and polymer layers, followed by precise photoresist layer patterning to create metal features of varying heights and sizes using electroplating processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If electroplating process is used to form metal bumps, then metal features can be formed efficiently, but larger-sized bumps are plated faster than smaller-sized bumps resulting in non-uniform bump heights
Solution Approach 1:
The patent divides the bump formation process into multiple sequential electroplating stages. Each stage uses different plating conditions (current density, time, chemistry) to deposit metal layers with controlled growth rates. This segmentation allows the plating process to adapt to varying bump sizes, preventing larger bumps from growing excessively fast while ensuring smaller bumps reach the required height.
Solution Approach 2:
The patent implements dynamic control of electroplating parameters throughout the process. Current density, plating time, and electrolyte composition are adjusted between stages based on the specific requirements of different bump sizes. This dynamic adjustment enables the system to maintain uniform bump heights across the wafer despite variations in initial bump dimensions.
2Adaptability or versatility
If different sized bumps are formed on the same wafer, then design flexibility is improved, but controlling bump heights becomes difficult affecting manufacturing yield
Solution Approach 1:
The patent applies different plating conditions to different regions of the wafer during the electroplating process. By localizing specific plating parameters (current density, time, chemistry) to specific bump locations, the process can accommodate varying bump sizes and height requirements across the same wafer. This local quality approach enables design flexibility while maintaining precise height control for each bump type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables controlled formation of metal features with different heights and sizes, improving chip integration and yield by allowing high-density interconnect routing in semiconductor packages.
Implementation Method 1
sputtering a metal material on the exposed surfaces of the polymer layer and the a plurality of metal bond pads to form the seed layer
Implementation Method 2
forming a first metal feature of a first height in the first opening; forming a second metal feature of a second height in the second opening
Data Source
AI summary
The present disclosure provides a method for forming a semiconductor package and a semiconductor package. The method comprises providing a semiconductor wafer with at least one semiconductor device formed thereon, the at least one semiconductor device comprising a plurality of metal bond pads formed on the semiconductor wafer. The method further comprises forming a first photoresist layer having a first opening directly above at least a portion of a first metal bond pad; forming a first metal feature of a first height in the first opening; removing the first photoresist layer; forming a second photoresist layer having a second opening directly above at least a portion of the second metal bond pad; forming a second metal feature of a second height in the second opening; and removing the second photoresist layer. Using the method, metal bumps having different heights and different sizes can be formed in a controlled manner.