Semiconductor Bump With Multiple Vias For Reliability
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Solution Overview
Problem
Conventional wafer level chip scale packages face issues with interface cracks due to atomic migration and electromigration at high current/high frequency operations, leading to signal delay and distortion, and require improved contact reliability and thermal stress resistance.
Innovation Solution
A bump structure for semiconductor packages featuring a polymer layer with multiple vias on an electrode pad, an underbump metallurgy (UBM) with specific layer configurations, and a metal bump bonded to the UBM, which increases contact area and disperses current, reducing interface cracks and enhancing mechanical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single via bump structure is used, then the manufacturing process is simple, but interface cracks occur due to atomic migration and electromigration at high current/high frequency operations
Solution Approach 1:
The single via is divided into multiple vias (first via and second via) within the bump structure. This segmentation distributes the current flow paths and reduces current density at any single interface, thereby minimizing atomic migration and electromigration effects that cause interface cracks during high current/high frequency operations.
Solution Approach 2:
The bump structure transitions from a two-dimensional planar via to a three-dimensional multi-via configuration. The via extends vertically through the substrate thickness and branches horizontally into multiple pathways (first via and second via), adding spatial dimensions to dissipate stress and current density more effectively.
2Reliability
If the contact area between electrode pad and metal bump is increased, then contact reliability improves, but the manufacturing process becomes more complex
Solution Approach 1:
The polymer layer is formed with a via that is nested within it, creating a hierarchical structure where the via is contained within the polymer matrix. This nested configuration increases the effective contact area between the electrode pad and metal bump while maintaining a compact overall structure that can be integrated into existing manufacturing processes.
3Speed
If high integration density and high performance are achieved, then operating speed increases, but signal delay and distortion worsen
Solution Approach 1:
The current path is segmented into multiple parallel via pathways (first via and second via), which reduces the current density in each individual path. This segmentation decreases resistive heating and electromagnetic interference, thereby reducing signal delay and distortion that typically worsen with high-speed operations in densely integrated packages.
Data Source
AI summary
A bump for a semiconductor package forms a polymer layer having multiple vias on an electrode pad above a semiconductor chip to increase an electrical contact area between the electrode pad and a metal bump. Further, the bump forms a polymer layer having multiple vias on a redistribution electrode pad to increase a surface area of an electrode interconnection. The multiple vias increase electrical and mechanical contact areas, thereby preventing current crowding and improving joint reliability. The bump for a semiconductor package may further comprise a stress relaxation layer at the lower portion of the bump.