Semiconductor Package Bump Pad Structure Against Cracks and Peeling
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Solution Overview
Problem
Semiconductor packages with compact size and weight reduction are prone to stress-induced cracks and peeling of the lower bump pad and redistribution insulating layer due to external stress and heat generation, leading to reliability issues.
Innovation Solution
Incorporating a first conductive barrier layer surrounding the side surfaces of the lower bump pad and a second conductive barrier layer on the cover portion, both with excellent adhesion to the redistribution insulating layer, to prevent crack propagation and peeling, while ensuring stress distribution and adhesion between the lower bump pad and the external connection bump.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If the semiconductor package is designed with compact size and weight reduction, then the portability and integration of electronic devices are improved, but stress concentration occurs on the lower bump pad and redistribution insulating layer leading to cracks and peeling
Solution Approach 1:
A lower bump pad structure is introduced as an intermediary component between the external connection bump and the redistribution insulating layer. This lower bump pad includes a contact portion that directly contacts the external connection bump and a cover portion that surrounds the contact portion, serving as a stress-distributing mediator that prevents direct stress concentration on the redistribution insulating layer.
Solution Approach 2:
The lower bump pad is designed with non-uniform local structure where the contact portion has different properties than the cover portion. The contact portion is optimized for direct mechanical and electrical contact with the external connection bump, while the cover portion provides stress distribution and protection, creating localized functional zones that address different requirements.
2Power
If the semiconductor package generates heat during operation, then the processing capacity is improved, but heat-induced peeling occurs between the lower bump pad and redistribution insulating layer
Solution Approach 1:
The lower bump pad acts as a thermal intermediary layer between the heat-generating external connection bump and the redistribution insulating layer. This intermediate structure helps manage thermal stress distribution, preventing heat-induced peeling while allowing the package to maintain high processing capacity.
3Productivity
If external stress is applied to the compact semiconductor package, then the integration density is improved, but crack propagation occurs along the side surface of the lower bump pad
Solution Approach 1:
The lower bump pad is designed with differentiated local regions where the cover portion provides enhanced structural strength and crack resistance along the side surfaces, while the contact portion maintains optimal electrical and mechanical contact properties. This local quality differentiation allows the structure to resist crack propagation under external stress.
Solution Approach 2:
The cover portion of the lower bump pad is designed to surround and protect the contact portion beforehand, creating a cushioning effect that prevents crack initiation and propagation along the side surfaces before external stress can cause damage.
Data Source
AI summary
A semiconductor package includes a semiconductor chip, a redistribution insulating layer having a first opening, and an external connection bump including a first portion filling the first opening. A lower bump pad includes a first surface and a second surface opposite the first surface. The first surface includes a contact portion that directly contacts the first portion of the external connection bump and a cover portion surrounding side surfaces of the contact portion. A first conductive barrier layer surrounds side surfaces of the lower bump pad and is disposed between the lower bump pad and the redistribution insulating layer. A redistribution pattern directly contacts the second surface of the lower bump pad and is configured to electrically connect the lower bump pad to the semiconductor chip.