Semiconductor Package Bump Pad Structure for Stress Crack Reduction
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Solution Overview
Problem
Miniaturization of semiconductor packages leads to increased susceptibility to damage from external stress due to reduced distance between connection pads and smaller terminal sizes, resulting in potential cracks and deterioration of adhesive forces between connection components.
Innovation Solution
A semiconductor package design featuring a redistribution insulating layer, an external connection bump, a lower bump pad with a seed layer, and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip, where the surface of the seed layer is coplanar with the external connection bump, enhancing mechanical stability and bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the distance between connection pads is reduced to accommodate miniaturization, then the semiconductor package volume is reduced, but the connection pad and connection terminal become more susceptible to damage from external stress
Solution Approach 1:
The patent introduces a redistribution insulating layer and redistribution pattern that routes signals through multiple layers rather than directly between adjacent pads. This three-dimensional redistribution structure allows the connection pads to be positioned closer together while maintaining adequate signal path lengths and stress distribution, effectively decoupling the pad spacing from the electrical connection length.
Solution Approach 2:
The redistribution insulating layer acts as an intermediary between the connection pads, providing a structured medium that distributes mechanical stress and protects the underlying connection terminals. The insulating layer with its embedded redistribution pattern serves as a buffer zone that prevents direct stress transmission between adjacent pads.
2Volume of moving object
If the connection terminal size is reduced for miniaturization, then the semiconductor package is smaller, but the adhesive force between connection components deteriorates
Solution Approach 1:
The connection structure employs composite material layers including the redistribution insulating layer, seed layer, and redistribution pattern. This composite structure combines materials with different mechanical properties to enhance overall bond strength while maintaining small terminal dimensions. The insulating layer provides mechanical support and stress distribution, while the conductive redistribution pattern ensures electrical connectivity.
Solution Approach 2:
The patent transitions from two-dimensional direct pad-to-pad connections to a three-dimensional structure with vertical stacking of insulating layers and conductive patterns. This dimensional change allows small terminal sizes to maintain adequate bonding area through vertical redistribution paths and multi-layer attachment surfaces.
3Volume of moving object
If miniaturization is implemented, then the semiconductor package volume is reduced, but crack formation increases due to stress concentration
Solution Approach 1:
The redistribution insulating layer serves as a stress-distributing intermediary that prevents concentration of mechanical stresses at critical interfaces. By embedding the redistribution pattern within this compliant insulating medium, the structure absorbs and distributes external stresses uniformly, preventing crack initiation and propagation in the miniaturized package.
Solution Approach 2:
The patent incorporates the redistribution insulating layer and redistribution pattern as pre-designed stress management features before external stress is applied. This proactive structural design cushions against future mechanical stresses, preventing crack formation in advance rather than reacting to damage after it occurs.
Data Source
AI summary
A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.