Semiconductor Device Wafer-Level Bump Pad Testing Circuit
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Solution Overview
Problem
Conventional semiconductor devices face inefficiencies in testing bump pads at the wafer level, leading to increased test time and the inability to detect defects early, which results in higher costs and inefficient manufacturing processes.
Innovation Solution
A test circuit that includes a connection control unit to couple bump pads during a test operation period and a test operation unit to control data input and output units for sequential transmission of test data through the coupled pads, allowing for rotational input of test data through a probe pad to minimize test time and detect defects at the wafer level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional testing methods are used for bump pads, then testing can be performed, but test time is excessively long and defects cannot be detected at wafer level
Solution Approach 1:
The testing process is segmented into wafer-level testing and post-packaging testing. The invention enables testing to be performed at the wafer level by providing test circuits directly on the wafer that can test bump pads before packaging, thereby reducing the need for lengthy post-packaging testing and enabling early defect detection.
Solution Approach 2:
Testing is performed preliminarily at the wafer level before packaging. The test circuits are integrated on the wafer and can test bump pads, interconnect structures, and other features before the wafer is packaged, allowing defects to be detected early in the manufacturing process.
2Measurement precision
If bump pads are tested after packaging, then defect detection is possible, but test time increases and manufacturing efficiency decreases
Solution Approach 1:
The testing dimension is changed from post-packaging to wafer level. By integrating test circuits on the wafer and enabling testing before packaging, the invention adds a new testing dimension that allows early defect detection without compromising manufacturing efficiency.
Solution Approach 2:
Test circuits are introduced as intermediary elements on the wafer that enable testing of bump pads and interconnect structures before packaging. These test circuits act as mediators between the bump pads and the testing equipment, allowing wafer-level testing to occur.
3Productivity
If wafer level testing is implemented, then test time is reduced and defects can be detected early, but additional test circuits and structures are required
Solution Approach 1:
The test circuits are designed to perform multiple testing functions. They can test bump pads, interconnect structures, and other features on the wafer, thereby reducing the need for separate dedicated test circuits for each feature and reducing overall test circuit complexity.
Solution Approach 2:
Testing functions are merged into the wafer-level test circuits. Instead of having separate testing equipment and processes for different features, the invention combines multiple testing capabilities into integrated test circuits on the wafer, reducing overall system complexity.
Data Source
AI summary
A semiconductor device includes a plurality of first pads, a plurality of data input and output units suitable for transmitting a data between a plurality of global lines and the plurality of first pads, respectively, a connection control unit suitable for coupling the plurality of first pads to each other in a test operation period, and a test operation unit suitable for controlling the plurality of data input and output units to transmit a test data in a set order through the plurality of first pads coupled to each other in the test operation period.