Semiconductor Package Conductive Bump Solder Resist Opening
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Solution Overview
Problem
Semiconductor packages fabricated using wafer-level multi-chip packaging experience warpage due to material mismatch, leading to poor bump shape and bonding issues during the C4 bump process, resulting in reduced bonding strength and increased process yield loss.
Innovation Solution
The use of enlarged solder resist opening patterns on the package substrate provides additional space for conductive bumps, increasing their contact area and bonding strength, while maintaining a low standoff, thereby addressing warpage-related issues and improving bonding quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level multi-chip packaging is used, then productivity is improved, but manufacturing precision deteriorates due to warpage causing poor bump shape
Solution Approach 1:
The patent applies local quality by creating non-uniform solder resist opening patterns where the opening size varies based on location. Specifically, openings in regions prone to warpage-induced bump deformation are enlarged to provide additional space for bump formation, while other regions maintain standard opening sizes. This localized adjustment compensates for warpage effects without requiring changes to the entire packaging process.
Solution Approach 2:
The patent changes the geometric parameters of the solder resist opening patterns to address warpage issues. By adjusting the opening size and shape parameters in specific regions, the patent compensates for material mismatch warpage during the C4 bump process, ensuring adequate bump formation space while maintaining overall packaging productivity.
2Strength
If solder resist opening patterns are enlarged, then bonding strength is improved, but device complexity increases
Solution Approach 1:
The patent implements local quality by differentiating solder resist opening patterns based on their location and functional requirements. Enlarged openings are strategically placed in regions requiring enhanced bonding capability, while other regions maintain standard patterns. This selective approach improves bonding strength where needed without unnecessarily complicating the entire solder resist design.
Data Source
AI summary
A semiconductor package includes a package substrate, an encapsulated semiconductor device, and a plurality of conductive bumps. The package substrate includes a device mounting region, a plurality of substrate pads and a solder resist layer. The encapsulated semiconductor device is disposed over the device mounting region and includes a plurality of device pads. The conductive bumps are connected between the plurality of substrate pads and the plurality of device pads through the solder resist layer and includes a first conductive bump on a periphery of the device mounting region. A first contact area of the first conductive bump for contacting respective one of the substrate pads is substantially greater than a second contact area of the first conductive bump for contacting respective one of the device pads.