Semiconductor Package Bump Layout for Warpage Overflow Control
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Solution Overview
Problem
Semiconductor chips with warpage can lead to non-uniform distances between the chip and the mount surface, causing connection members to overflow and potentially result in semiconductor device failure. Additionally, excessive miniaturization of pads and connection members can lead to defects such as cracks.
Innovation Solution
A semiconductor package design that includes a semiconductor substrate with connection pads and bumps, where the bumps consist of an extension bump and a non-extension bump. The extension bump features an extension seed layer and a conductive pillar, with the seed layer extending in a specific direction to manage connection member overflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the sizes of pads and connection members are reduced to accommodate warpage, then the distance uniformity improves, but connection members may crack due to excessive miniaturization
Solution Approach 1:
The patent applies local quality by creating two distinct types of connection bumps with different structures: extension bumps with elongated seed layers for pads requiring extended connection, and non-extension bumps with conventional structures for standard pads. This localized differentiation allows each connection member to be optimally sized and structured for its specific function, preventing cracks while maintaining distance uniformity across the chip surface.
Solution Approach 2:
The patent changes the geometric parameters of connection members by varying the seed layer dimensions. Extension bumps have seed layers with length L1 greater than the pad pitch P, while non-extension bumps have seed layers with length L2 less than or equal to P. This parameter variation allows connection members to maintain adequate size and strength while achieving uniform distance from the chip surface despite warpage.
2Object-affected harmful factors
If connection members are miniaturized to prevent overflow, then overflow contact between adjacent members is reduced, but cracks may occur in the connection members
Solution Approach 1:
The patent implements local quality by differentiating connection bump structures based on their specific requirements. Extension bumps use elongated seed layers that extend beyond adjacent pads to control solder flow direction, while non-extension bumps use compact structures. This localized structural differentiation prevents overflow contact in extension bumps while maintaining adequate size to prevent cracks in all connection members.
Solution Approach 2:
The patent converts the potential harm of solder overflow into a beneficial directional flow control mechanism. By extending the seed layer in specific directions, the overflow solder is guided along the extended seed layer away from adjacent pads, transforming what would be a harmful overflow into a controlled filling process that enhances connection reliability without causing defects.
3Object-affected harmful factors
If extension seed layer extends in specific direction, then connection member overflow is controlled, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the connection bumps into two distinct categories: extension bumps with elongated seed layers and non-extension bumps with conventional structures. This segmentation allows the complex extended structure to be applied only where needed for overflow control, while simpler structures are used elsewhere, thereby managing overall manufacturing complexity through selective application of different designs.
Solution Approach 2:
The patent inverts the conventional approach by making the extension bump the specialized variant rather than the standard. Instead of assuming all bumps should be uniform and adding complexity only where needed, the design establishes the extended seed layer structure as the primary solution for overflow control, with non-extension bumps serving as the simplified alternative for areas where overflow is less of a concern.
Data Source
AI summary
A semiconductor package includes a semiconductor substrate, connection pads on a bottom surface of the semiconductor substrate, and connection bumps respectively on the connection pads, wherein the connection bumps include an extension bump and a non-extension bump, wherein the extension bump includes an extension seed layer on a respective one of the connection pads and a first conductive pillar on the extension seed layer, and wherein the extension seed layer longitudinally extends in a first extension direction.