Semiconductor Device Buried Diffusion Layer Overvoltage Protection
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Solution Overview
Problem
Conventional semiconductor devices face issues with overvoltage protection, as the N-type buried region formation leads to current concentration and heat generation, potentially breaking the PN junction region, and the widening of this region to improve withstand voltage characteristics results in inefficient chip layout due to increased distance between the drain and isolation regions.
Innovation Solution
A semiconductor device structure featuring a buried diffusion layer of one conductivity type and an overlapping buried diffusion layer of opposite conductivity type, where the breakdown voltage of the first junction region is lower than the second junction region on the current path, allowing the first junction to break down ahead of the second, preventing semiconductor element damage from overvoltage, and enabling adjustable breakdown voltage and efficient chip layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the N-type buried region is formed to have the same width as the drain region for overvoltage protection, then the breakdown voltage characteristic is improved, but current concentrates on the PN junction region causing heat generation and potential breakdown
Solution Approach 1:
The patent applies local quality by creating a non-uniform width profile for the N-type buried region. The width varies along the longitudinal direction, being narrower at certain positions and wider at others. This local variation allows different segments of the PN junction region to distribute the breakdown current differently, preventing concentration at any single point while maintaining overall overvoltage protection capability.
2Reliability
If the N-type buried region is extended over a wider region to prevent current concentration, then the withstand voltage characteristic is improved, but the distance between drain region and isolation region increases reducing element formation efficiency
Solution Approach 1:
The patent uses local quality by varying the width of the N-type buried region along its length rather than extending it uniformly. This allows the region to provide adequate overvoltage protection where needed while maintaining a compact overall footprint that preserves efficient element formation and minimizes the distance between drain region and isolation region.
Solution Approach 2:
The patent addresses the spatial constraint by introducing variation in the longitudinal dimension rather than simply expanding in the lateral dimension. By controlling the width along the length of the buried region, the design achieves improved withstand voltage characteristics without proportionally increasing the chip area or reducing element formation efficiency.
3Ease of manufacture
If the N-type buried region is formed with uniform width for simple manufacturing, then the manufacturing process is simplified, but the breakdown current concentrates causing heat generation
Solution Approach 1:
The patent implements local quality through a multi-stage diffusion process that creates different width segments in the N-type buried region. This is achieved by performing separate diffusion operations with different masking patterns, allowing precise control of the width profile. While slightly more complex than uniform diffusion, the process remains manufacturable and effectively distributes breakdown current to reduce heat generation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure effectively protects semiconductor elements from overvoltage by prioritizing the breakdown of the first junction region, reducing the risk of PN junction region damage and heat generation, while allowing for efficient element arrangement and miniaturization of the chip.
Implementation Method 1
a breakdown voltage of a first junction region between the buried diffusion layer of the one conductivity type and the buried diffusion layer of the opposite conductivity type is lower than a breakdown voltage of a second junction region formed on a current path of a semiconductor element
Data Source
AI summary
According to a semiconductor device of an embodiment of the present invention, a P-type buried diffusion layer is formed across a substrate and an epitaxial layer. An N-type buried diffusion layer is formed in the P-type buried diffusion layer. An overvoltage protective PN junction region is formed below an element formation region. A breakdown voltage of the PN junction region is lower than a source-drain breakdown voltage. This structure prevents a breakdown current from concentratedly flowing into the PN junction region and protects the semiconductor device from overvoltage.