Semiconductor Device With Buried Insulating Patterns For High Voltage
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high operating voltages without additional discrete devices, and existing technologies struggle to provide stable high-voltage capabilities while maintaining efficient power consumption and performance.
Innovation Solution
A semiconductor device design featuring a substrate with a channel region, gate insulating layer, gate electrode, buried insulating patterns, and source/drain regions, where the buried insulating patterns are strategically placed to enhance breakdown voltage and reduce threshold voltage mismatch, achieved through a manufacturing process involving epitaxial growth and ion implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional discrete devices are used to generate high operating voltages, then high voltage capability is achieved, but device complexity increases
Solution Approach 1:
The patent merges the high voltage generation function into the semiconductor device structure itself by forming a drain region extending to a deep well region, eliminating the need for external discrete devices. The gate structure and insulating layers are integrated to work together for high voltage operation, combining multiple functions into a unified device architecture.
Solution Approach 2:
The patent extends the drain region in the vertical dimension to reach the deep well region, utilizing depth as an additional spatial dimension to achieve high voltage breakdown characteristics. This vertical extension allows the device to withstand high voltages without requiring additional external components.
2Reliability
If conventional structures are used, then manufacturing is simpler, but breakdown voltage is insufficient
Solution Approach 1:
The patent segments the semiconductor structure into multiple functional regions: a shallow well region, a deep well region, and intermediate regions with different doping concentrations. This segmentation allows each region to be optimized for specific functions (threshold voltage control, breakdown voltage enhancement) while being manufactured through sequential processing steps.
Solution Approach 2:
The patent applies different doping concentrations and impurity types to different spatial locations: high concentration in the drain region for low threshold voltage, and controlled concentration in the well regions for high breakdown voltage. This local quality variation enables simultaneous optimization of different device parameters in different regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables semiconductor devices to operate at high voltages with improved breakdown voltage characteristics and reduced threshold voltage mismatch, enhancing current characteristics and power efficiency.
Implementation Method 1
forming an epitaxial semiconductor layer for filling the recess space
Implementation Method 2
forming a first source/drain region in a part of the substrate using the mask layer as an implantation mask
Data Source
AI summary
A semiconductor device having a high and stable operating voltage and a method of manufacturing the same, the semiconductor device including: a substrate having an active region including a channel region; a gate insulating layer that covers a top surface of the active region; a gate electrode that covers the gate insulating layer on the top surface of the active region; buried insulating patterns in the channel region of the active region at a lower side of the gate electrode and spaced apart from a top surface of the substrate; and a pair of source/drain regions in the substrate at both sides of each of the buried insulating patterns and extending from the top surface of the substrate to a level lower than that of each of the buried insulating patterns.