Semiconductor Device Breakdown Voltage via Localized Buried Layers
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Solution Overview
Problem
Current methods for increasing breakdown voltage in Bipolar-CMOS-DMOS semiconductor devices are not cost-effective, such as increasing the thickness of the epitaxial layer or replacing the Si substrate with a semiconductor-on-insulator (SOI).
Innovation Solution
The semiconductor device incorporates a substrate with a first conductive type well region and second conductive type buried layers disposed at opposite sides, a second conductive type third buried layer, and a doped region, along with a gate structure and contact plugs, without increasing the epitaxial layer thickness or replacing the Si substrate, to enhance breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the epitaxial layer is increased to increase breakdown voltage, then the breakdown voltage is improved, but the manufacturing cost increases
Solution Approach 1:
The patent introduces a first conductive type well region and multiple second conductive type buried layers at specific locations within the semiconductor device. These localized doped regions create a reduced surface field structure that specifically enhances breakdown voltage at critical areas without requiring uniform thickening of the entire epitaxial layer, thus improving reliability while controlling manufacturing costs.
Solution Approach 2:
The patent modifies the electrical parameters by introducing specific conductive type regions (first conductive type well and second conductive type buried layers) with controlled doping concentrations. This changes the electric field distribution and carrier concentration parameters locally, achieving higher breakdown voltage through parameter optimization rather than structural scaling.
2Reliability
If the Si substrate is replaced with semiconductor-on-insulator (SOI) to increase breakdown voltage, then the breakdown voltage is improved, but the manufacturing cost increases
Solution Approach 1:
Instead of replacing the entire Si substrate with expensive SOI structure, the patent introduces localized second conductive type buried layers at specific positions (first, second, and third buried layers) within the existing Si substrate. This localized modification achieves the breakdown voltage enhancement without the high cost of complete substrate replacement.
Solution Approach 2:
The patent uses conventional Si substrate with localized doped regions rather than expensive SOI substrate. This approach uses cost-effective materials and processes (standard ion implantation or diffusion) to achieve the desired performance, avoiding the high manufacturing costs associated with SOI technology.
3Reliability
If multiple buried layers and well regions are added to increase breakdown voltage, then the breakdown voltage is improved, but the device complexity increases
Solution Approach 1:
The patent combines multiple functional elements into a unified structure: the first conductive type well region serves as both a structural element and an electrical component, while the second conductive type buried layers (first, second, and third) work together to create the reduced surface field effect. This merging of functions reduces the need for separate components and simplifies the overall device architecture.
Solution Approach 2:
The introduced well regions and buried layers serve multiple functions simultaneously: they enhance breakdown voltage through field reduction, provide electrical isolation, control carrier distribution, and maintain compatibility with standard CMOS fabrication processes. This multi-functionality reduces the need for additional specialized structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the breakdown voltage of the semiconductor device to support higher operation voltages beyond 100V while maintaining cost-effectiveness and forming a reduced surface field structure to further enhance voltage breakdown.
Implementation Method 1
a first conductive type first well region disposed in the substrate and the epitaxial layer; a second conductive type first buried layer and a second conductive type second buried layer disposed in the substrate and the epitaxial layer, wherein the second conductive type first buried layer and the second conductive type second buried layer are disposed at opposite sides of the first conductive type first well region
Implementation Method 2
A second conductive type third buried layer is disposed in the first conductive type first well region and/or the first conductive type second well region. A second conductive type doped region is disposed in the first conductive type second well region
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer; a first conductive type first well region disposed in the substrate and the epitaxial layer; a second conductive type first buried layer and a second conductive type second buried layer disposed at opposite sides of the first conductive type first well region, respectively; a first conductive type second well region disposed in the epitaxial layer and being in direct contact with the first conductive type first well region; a second conductive type third buried layer disposed in the first conductive type first well region and/or the first conductive type second well region; a second conductive type doped region disposed in the first conductive type second well region; a gate structure; a drain contact plug; and a source contact plug.