Semiconductor Device With Buried Planar Wiring Layer
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Solution Overview
Problem
Conventional semiconductor devices face issues with uneven current distribution and increased wire resistance due to the miniaturization of power transistors, leading to reliability concerns and reduced lifespan of semiconductor elements.
Innovation Solution
A semiconductor device structure featuring a trench-formed semiconductor substrate with a planar wiring layer embedded under the semiconductor element formation region, connected to a conductor that functions as a source or drain, reducing wire resistance and suppressing variations in current distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the area of each semiconductor element is decreased to enable miniaturization, then the integration density increases, but the wire width decreases and wire resistance increases
Solution Approach 1:
The patent introduces a planar wiring layer embedded in the semiconductor substrate underneath the semiconductor elements, adding a vertical dimension to the wiring structure. This buried planar wiring layer provides an alternative current path that is decoupled from the surface wire dimensions, allowing surface wires to be miniaturized while the subsurface planar layer maintains adequate cross-sectional area for low resistance.
2Area of stationary object
If the wire width is decreased due to reduced semiconductor element area, then the layout density increases, but the wire resistance increases causing uneven voltage distribution
Solution Approach 1:
The planar wiring layer acts as an intermediary conductive path between the power supply and the semiconductor elements. Instead of relying solely on narrow surface wires that cause voltage drops, the current flows through the broader planar layer embedded in the substrate, which serves as a low-impedance intermediary that equalizes voltage distribution across all elements.
3Reliability
If conventional LDMOSFET structure is used with drift region, then the withstand voltage is improved, but the device area increases limiting miniaturization
Solution Approach 1:
The patent transitions from a lateral drift region structure to a vertical buried layer structure. Instead of extending the drift region laterally to increase breakdown voltage, the invention uses a vertically embedded planar wiring layer in the substrate that provides both electrical connection and voltage withstand capability, freeing up lateral space for miniaturization.
Data Source
AI summary
A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.