Semiconductor Burn-In Test Thermal Runaway Control
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Solution Overview
Problem
Existing semiconductor burn-in test methods face challenges in controlling temperature during the burn-in test, particularly for devices that consume high current, risking thermal runaway, and existing techniques are not applicable to devices receiving a clock signal directly from a test apparatus.
Innovation Solution
A semiconductor device configuration that includes a temperature sensor, scan control circuit, clock control circuit, pattern generation circuit, and logic circuit, which generates scan chain clock signals based on external clock signals and temperature measurements to control temperature variation during the burn-in test, suppressing thermal runaway.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If temperature control is implemented during burn-in test, then thermal runaway is suppressed, but device complexity increases
Solution Approach 1:
The clock control circuit is designed to serve dual purposes: it controls the clock signal frequency during burn-in testing to manage temperature, and also functions as part of the device's normal operating clock distribution system. This multi-functionality allows temperature control without adding dedicated separate circuitry, thereby suppressing thermal runaway while minimizing increases in device complexity.
Solution Approach 2:
The invention controls temperature by dynamically adjusting the frequency parameter of the clock signal based on real-time temperature feedback. The clock control circuit modifies the clock frequency to correlate with temperature conditions, creating a passive thermal management mechanism that achieves reliability improvement through parameter modulation rather than active cooling/heating circuits.
2Temperature
If clock frequency is varied to control temperature, then temperature control is achieved, but test precision is reduced
Solution Approach 1:
The clock distribution system is segmented into multiple independent clock domains, with dedicated clock control circuits for each scan chain. This segmentation allows individualized frequency control for each chain based on its specific thermal characteristics, enabling precise temperature management while maintaining accurate test measurements through chain-specific optimization rather than blanket frequency adjustment.
Solution Approach 2:
The system implements a feedback mechanism where temperature sensor data is continuously monitored and fed back to the clock control circuit. This feedback loop enables real-time adjustment of clock frequency in response to actual temperature conditions, achieving effective temperature control while maintaining test precision through adaptive rather than fixed frequency modulation.
3Productivity
If multiple scan chains are activated, then test productivity increases, but temperature control becomes difficult
Solution Approach 1:
The clock control system is designed to dynamically adjust the frequency of each scan chain's clock signal in real-time based on temperature feedback. This dynamic control allows multiple scan chains to operate simultaneously at optimized frequencies, maintaining high test productivity while actively managing the thermal load generated by parallel chain operation through adaptive frequency modulation.
Solution Approach 2:
The invention changes the operational parameters (clock frequency) of each scan chain individually based on temperature conditions. By modulating the frequency parameter of clock signals supplied to multiple scan chains, the system can increase productivity through parallel operation while controlling the aggregate thermal output through parameter adjustment, allowing more chains to operate at lower frequencies rather than fewer chains at high frequency.
Data Source
AI summary
A semiconductor device includes a temperature sensor, a scan control circuit which generates scan chain selection information in accordance with a measurement result of the temperature sensor, a clock control circuit which generates one or more scan chain clock signals based on an external clock signal and the scan chain selection information, a pattern generation circuit which generates a test pattern, and a logic circuit which includes a plurality of scan chains and which receives the scan chain clock signals and the test pattern. The clock control circuit generates the scan chain clock signal in association with each scan chain. During a burn-in test, the logic circuit captures the test pattern into the scan chain associated with the scan chain clock signal.