Semiconductor Bus Access Control via Probability-Weighted Rights
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Solution Overview
Problem
Existing semiconductor devices face inefficiencies in memory access due to varying use rates of access rights, leading to congestion on the bus and decreased memory efficiency, as the number of granted access rights is not effectively managed based on the probability of their usage.
Innovation Solution
A semiconductor device with an access control unit that manages the number of grantable access rights based on a weight representing the probability of their usage, allowing for more efficient allocation and reuse of access rights, thereby reducing congestion and improving memory efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the access right is granted to the request issuance control unit, then the memory access is enabled, but the bus congestion occurs due to multiple access requests
Solution Approach 1:
The patent introduces a weight parameter (w) associated with each access right that represents the probability of the access right being used. The access control unit manages the number of grantable access rights based on this weight parameter, dynamically adjusting the allocation to prevent bus congestion while maintaining memory access efficiency. This parameter-based approach allows the system to optimize the balance between enabling memory accesses and preventing request congestion on the bus.
2Productivity
If the number of grantable access rights is increased, then the memory efficiency is improved, but the bus congestion increases
Solution Approach 1:
The patent uses a weight parameter (w) that represents the probability of an access right being used. The access control unit calculates the number of grantable access rights based on this weight parameter, allowing dynamic adjustment of the number of active access rights. This enables the system to increase memory efficiency when needed while preventing bus congestion by limiting the number of simultaneously active access rights according to their usage probabilities.
Solution Approach 2:
The patent implements a feedback mechanism where the access control unit monitors the actual usage of access rights and adjusts the number of grantable access rights accordingly. When access rights are returned (indicating they were not used), the control unit increases the number of grantable access rights. This feedback loop ensures the system optimizes the balance between memory efficiency and bus congestion prevention in real-time.
3Productivity
If the access right is returned quickly, then the resource utilization is improved, but the latency increases due to the time required for return processing
Solution Approach 1:
The patent applies preliminary action by having the request issuance control unit prepare for access right return before the actual return occurs. The control unit maintains a counter that tracks the number of granted access rights and is configured to immediately increase the number of grantable access rights when an access right is returned. This preparedness allows the system to quickly reallocate resources without significant latency, as the mechanism is already in place to handle the return scenario.
Data Source
AI summary
A master issues an access request to the memory. The memory controller receives the access request via a bus. An access control unit controls an output of the access request issued by the master to the memory controller by the granting an access right. The access control unit manages a number of grantable rights indicating a number to which the access rights can be granted based on a weight of 0 or more and less than 1 according to a probability that the granted access right is used, and grants the access right within a range of the number of grantable rights.