Semiconductor Bus Control for Cache Write-Back Latency
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Solution Overview
Problem
Existing semiconductor devices face challenges in controlling access requests to a memory controller when a cache is arranged between masters and the memory controller, leading to difficulties in guaranteeing latency due to buffer occupation by cache write-back operations.
Innovation Solution
The implementation of a central bus control system that separates access control for read and write requests, monitoring buffer and cache conditions to dynamically adjust access rights and sub-slots, ensuring efficient scheduling and latency management by granting access rights exclusively in different periods based on cache availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a cache is arranged between each master and the memory controller, then data access speed is improved, but the buffer of the memory controller may be occupied by writing back of the cache, making it difficult to control access requests and guarantee latency
Solution Approach 1:
The patent segments the access control into two independent parts: (1) access control for read requests from masters to the memory controller, and (2) access control for write-back requests from the cache to the memory controller. This segmentation is achieved by providing separate control circuits: a first control circuit that controls access rights for read requests based on buffer free situations, and a second control circuit that controls access rights for write-back requests based on cache free situations. This allows independent management of read and write access paths, preventing write-back operations from blocking read request processing.
Solution Approach 2:
The patent introduces separate control circuits as intermediary components between the cache system and the memory controller. The first control circuit acts as an intermediary for read requests, monitoring buffer status and granting access rights accordingly. The second control circuit acts as an intermediary for write-back requests, monitoring cache status and controlling write-back timing. These intermediary control circuits enable the memory controller to maintain buffer availability for read requests even when cache write-back operations are occurring.
2Ease of operation
If the central bus control system monitors the buffer inside the memory controller to control access rights, then access request control is improved, but if cache write-back occurs, the buffer may be occupied and control effectiveness is reduced
Solution Approach 1:
The control system is segmented into independent control paths: one for read requests and one for write-back requests. The first control circuit monitors buffer status specifically for read request management, while the second control circuit monitors cache status for write-back management. This segmentation ensures that read request control remains effective even when the buffer is occupied by write-back operations, as the two control circuits operate independently with separate status monitoring.
Solution Approach 2:
The patent implements feedback mechanisms in both control circuits. The first control circuit receives feedback from the buffer status (free situations) and adjusts access right granting for read requests accordingly. The second control circuit receives feedback from the cache status (free situations) and adjusts access right granting for write-back requests accordingly. This dual feedback system ensures that each control circuit makes decisions based on relevant status information, maintaining control effectiveness for its specific function regardless of the other path's buffer occupancy.
3Reliability
If access rights are granted based on buffer free situations, then buffer overflow is prevented, but access requests for low latency may not be accepted when the buffer is full
Solution Approach 1:
The patent segments the access control functionality into separate control circuits for different request types. The first control circuit handles read requests from masters and grants access rights based on buffer free situations, preventing buffer overflow. The second control circuit handles write-back requests from the cache and grants access rights based on cache free situations. This segmentation allows low-latency read requests to be accepted and processed independently of cache write-back buffer occupancy, as the first control circuit monitors buffer status specifically for read request admission control.
Solution Approach 2:
The patent applies different control strategies to different parts of the system: the first control circuit applies buffer-based admission control for read requests, while the second control circuit applies cache-based admission control for write-back requests. This local quality approach allows each control circuit to optimize for its specific function: preventing buffer overflow for reads while managing cache write-back timing, thereby accepting low-latency read requests even when write-back buffer space is limited.
Data Source
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AI summary
A master issues a write request and a read request. A memory controller includes a request buffer for storing the write and read request, and accesses a memory in accordance with the stored write and read request. A cache is arranged between the master and the memory controller. A first write request issue control unit is arranged in correspondence with a first write request bus coupling the first master and the cache. A second write request issue control unit is arranged in correspondence with a second write request bus coupling the cache and the memory controller. First and second central bus control systems grant an access right to the first and second write request issue control units in accordance with a free situation of the cache and a fee situation of the request buffer, respectively. A read request issue control unit arranged in a manner corresponding to a read request bus, the second central bus control system configured to, using said read request issue control unit, control output of the read request issued by the first master to the memory controller in accordance with a free situation of the request buffer. The first write request issue control unit receives the write request issued from the master, and outputs the received write request in response to granting of the access right from the first central bus control system. The cache caches the write request output from the first write request issue control unit. The second write request issue control unit receives the write request from the cache, and outputs the received write request to the memory controller in response to granting of the access right from the second central bus control system.