Semiconductor Power Module Bus Layout for High Current and Low Inductance

The patent divides the power module into multiple independent chip units (first power chip, second power chip, third power chip, fourth power chip) that can be connected in parallel. Each chip is mounted on a separate substrate region with its own conductive paths, allowing current to be distributed across multiple smaller units rather than requiring a single large chip or tightly coupled parallel configuration, thereby reducing overall inductance while maintaining current output capability.

The patent employs a three-dimensional layout where power chips are arranged in multiple layers and directions on the substrate. The conductive regions extend in both first and second directions, creating a spatial distribution that reduces the effective loop area and inductance while accommodating multiple chips in a compact footprint, thus improving current capability without proportionally increasing module size.

The patent segments the current paths into multiple independent conductive regions on the substrate, each serving a specific power chip. This segmentation allows current from multiple chips to flow through separate, optimized paths that minimize loop areas, thereby reducing the cumulative stray inductance while maintaining high current output capability through parallel connection.

The patent optimizes the local conductive path geometry around each power chip, creating short and direct connection paths between the chips and the external terminals. The conductive regions are specifically shaped and positioned to minimize the enclosed loop area for each current path, which directly reduces stray inductance at the local level while supporting high current output.