Semiconductor Multilayer Bus Memory Access Arbitration
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Solution Overview
Problem
In semiconductor devices with multilayer bus configurations, it is challenging to prevent competition among bus masters accessing the same memory, leading to increased processing time and inefficiencies in software development, as developers must manually manage memory access to avoid conflicts.
Innovation Solution
The semiconductor device employs a management table with group IDs and IDs to allocate process regions, where group IDs group candidate regions by memory characteristics, and IDs are set for tasks to avoid competition, allowing the operating system to dynamically allocate resources and prioritize tasks based on their requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple bus masters access the same memory simultaneously, then the system can achieve parallel processing capability, but competition occurs leading to increased processing time
Solution Approach 1:
The patent applies preliminary action by pre-defining process regions and candidate regions in the memory before tasks are executed. The operating system预先 allocates specific memory regions to different tasks and establishes arbitration rules in advance. When bus masters need to access memory, they follow the pre-established allocation scheme, which prevents competition before it occurs and eliminates the need for runtime arbitration, thus maintaining parallel processing capability while avoiding time loss from conflicts.
2Reliability
If developers manually manage memory access to avoid conflicts, then competition can be suppressed, but software development becomes difficult and inefficient
Solution Approach 1:
The patent implements self-service by enabling the operating system to automatically manage memory resource allocation and arbitration. The OS maintains a management table that tracks process regions and candidate regions, and automatically arbitrates memory access requests from multiple bus masters without requiring developer intervention. This automated self-management mechanism ensures reliable competition suppression while freeing developers from complex memory management tasks, thereby improving software development efficiency.
3Adaptability or versatility
If the operating system dynamically allocates process regions from candidate regions, then resource utilization improves, but system complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory space into multiple candidate regions and allowing the operating system to dynamically allocate process regions from these segments. Each candidate region can be independently managed and assigned to different tasks based on their requirements. This segmentation approach provides flexible resource allocation while keeping the management structure organized and manageable, as the OS only needs to track regions rather than individual memory addresses, thus balancing adaptability with acceptable system complexity.
Data Source
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AI summary
The present disclosure provides a technique of suppressing competition of processes in a semiconductor device employing a multilayer bus configuration. A semiconductor device employing a multilayer bus configuration includes a control device controlling an access from each of bus maters to each memory, and a storage device for storing a corresponding relation between identification information identifying a storage region included in each memory and a group to which the storage region belongs. On the basis of an instruction of assuring a storage region including designation of a group, with reference to a corresponding relation between a group designated by an instruction and identification information from the corresponding relation stored in the storage device, the control device specifies one or more storage regions belonging to the designated group, assures the storage region used by a bus master on the basis of the use state of the specified storage region, and outputs information for accessing the assured storage region to the bus master corresponding to the instruction.