Semiconductor Bus Reassignment for 3D-Stack Signal Transfer

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Solution Overview

Problem

Semiconductor devices, such as DRAM, face inefficiencies due to unused read/write buses when switching between operation modes, particularly in 3D-stack packages, where separate wires for data and command/address transfers are needed, leading to increased chip size and complexity.

Innovation Solution

The semiconductor device is designed to be switchable between x8 and x4 operation modes by changing mask patterns during manufacturing, allowing unused read/write bus tracks to be reassigned for data transfer in 3D-stack packages, eliminating the need for additional wires and reducing chip size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate wires are provided for data transfer and command/address transfer in 3D-stack packages, then reliable signal transmission is ensured, but chip size and wiring complexity increase

Engineering Contradiction:

Improvesignal transmission reliabilityVSAvoidchip size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The read/write bus tracks are designed to serve multiple functions: they can transfer data signals during data operations and command/address signals during command operations. This multi-functionality eliminates the need for separate dedicated wires for command/address transfer, thereby reducing chip size while maintaining reliable signal transmission through proper timing control and buffer management.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically switches the function of read/write bus tracks based on operation mode. During x8 mode, all tracks transfer data; during x4 mode with 3D-stack, the bus structure adapts to transfer both data and command/address signals using the same physical infrastructure, with timing and control logic adjusted dynamically to ensure reliable transmission.

Inventive Principle:

Principle #15Dynamics

2Productivity

If read/write buses are dedicated to data transfer only, then data transfer efficiency is maximized, but command/address transfer requires additional wiring infrastructure

Engineering Contradiction:

Improvedata transfer efficiencyVSAvoidwiring infrastructure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The read/write bus tracks are designed as universal channels that can handle both data signals and command/address signals. This eliminates the need for separate dedicated wiring infrastructure for command/address transfer, reducing device complexity while maintaining data transfer efficiency through proper timing control that ensures data operations utilize the full bandwidth when needed.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the data transfer function and command/address transfer function into a single read/write bus infrastructure. By combining these functions and using timing control to manage signal priority and allocation, the system reduces wiring complexity while preserving data transfer efficiency through optimized bus arbitration and timing sequences.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If mask switching is used to change operation modes, then manufacturing flexibility is improved, but unused bus tracks remain idle in certain modes

Engineering Contradiction:

Improveoperation mode switching capabilityVSAvoidbus utilization efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The read/write bus tracks are designed with universal functionality to handle both data and command/address signals. This ensures that even when mask switching changes the operational configuration (e.g., from x8 to x4 mode), the previously unused bus tracks are reassigned to transfer command/address signals, eliminating idle resources and improving overall bus utilization efficiency while maintaining manufacturing flexibility.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Adaptability or versatility

If x4 operation mode is selected in 3D-stack package, then data transfer width is reduced, but unused bus tracks can be reassigned for command/address transfer

Engineering Contradiction:

Improveoperation mode flexibilityVSAvoidchip size

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

When x4 operation mode is selected in 3D-stack package, the system utilizes the same read/write bus infrastructure for both data transfer and command/address transfer. The bus tracks that would otherwise be unused in x4 mode are dynamically assigned to handle command/address signals, eliminating the need for additional dedicated wiring and thereby reducing chip size while maintaining operation mode flexibility.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11599484B2Semiconductor device having plural signal buses for multiple purposes

Publication Date: 2023.03.07 MICRON TECHNOLOGY INC

AI summary

Disclosed herein is a method for designing a semiconductor device, the method including: assigning a plurality of wiring tracks including first and second tracks; connecting a first data I/O circuit to a first data node of a first circuit by a first signal bus arranged on the first wiring track; connecting a second data I/O circuit to a second data node of the first circuit by a second signal bus arranged on the second wiring track when a first design mode is selected; and connecting the first data I/O circuit to a second circuit by a second signal bus arranged on the second wiring track when a second design mode is selected.