Semiconductor Bypass Capacitor Groove Structure

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Solution Overview

Problem

Existing semiconductor devices face challenges in reducing the area occupied by bypass capacitors on the semiconductor substrate while maintaining desired capacity, leading to increased manufacturing costs and potential fluctuations in power supply voltage.

Innovation Solution

The semiconductor device incorporates a configuration with capacitors having portions along concave portions on the substrate, allowing for a larger surface area per unit area and reducing the overall occupation area of the capacitor, thereby minimizing the size of the semiconductor substrate and manufacturing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a bypass capacitor is provided on a semiconductor substrate to reduce power supply voltage fluctuation, then power supply stability is improved, but the area occupied by the capacitor increases

Engineering Contradiction:
Improvepower supply stabilityVSAvoidcapacitor area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a planar capacitor structure to a three-dimensional structure by forming a groove in the semiconductor substrate and placing the capacitor within this groove. This vertical utilization of space allows the capacitor to occupy less surface area while maintaining the required capacitance value, directly resolving the contradiction between power supply stability and capacitor area occupation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If the area of the semiconductor substrate is reduced to lower manufacturing costs, then manufacturing cost is improved, but the capacity of the bypass capacitor is reduced

Engineering Contradiction:
Improvemanufacturing costVSAvoidcapacitor capacity
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

By forming a groove structure in the semiconductor substrate and placing the capacitor within this groove, the patent enables the capacitor to achieve the required capacitance value without increasing the substrate area. This three-dimensional configuration allows full utilization of the substrate area, enabling cost reduction through smaller substrate size while maintaining the necessary capacitor capacity for power supply stability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If the capacity of the bypass capacitor is increased to reduce power supply voltage fluctuation, then power supply stability is improved, but the area occupied by the capacitor increases

Engineering Contradiction:
Improvepower supply stabilityVSAvoidcapacitor area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The groove structure enables the capacitor to be formed with increased capacity without proportionally increasing the surface area occupation. By utilizing the vertical space within the groove, the capacitor can achieve higher capacitance values while maintaining a compact footprint, thus improving power supply stability without the penalty of excessive area occupation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11476263B2Semiconductor device
Publication Date: 2022.10.18 KIOXIA CORP
  • US11476263B2 patent drawing
  • US11476263B2 patent drawing
  • US11476263B2 patent drawing

AI summary

A semiconductor device includes: a semiconductor substrate; a first semiconductor layer; a first conductor; a first power supply line; a second power supply line; and a circuit. The semiconductor substrate has a first surface, a second surface facing the first surface, and a third surface disposed between the first surface and the second surface. The first semiconductor layer is disposed along the first surface from the third surface. The first conductor is disposed on the first semiconductor layer. The first power supply line is electrically connected to the first conductor. The second power supply line is electrically connected to the semiconductor substrate. The circuit is disposed on the semiconductor substrate and connected to the first power supply line and the second power supply line.