Semiconductor Bypass Interconnection Layout for Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor devices become more densely integrated, parasitic capacitances between interconnection lines increase, leading to reduced operation speed and refresh characteristics due to the decreasing distances between conductive patterns and contact plugs.
Innovation Solution
The implementation of a semiconductor device with an interconnection layout that includes bypass interconnection lines on a separate plane, connected to first and second interconnection lines via contact plugs, allowing for increased integration density while maintaining design margins and reducing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distances between interconnection lines and contact plugs are reduced to increase integration density, then the integration density increases, but the parasitic capacitances increase and operation speed decreases
Solution Approach 1:
The patent introduces a bypass interconnection line structure that utilizes a different spatial dimension (separate plane at different level) to route signals. This allows the bypass line to connect to first and second interconnection lines without being constrained by the two-dimensional layout, thereby reducing parasitic capacitance while maintaining high integration density.
Solution Approach 2:
The bypass interconnection line acts as an intermediary element that provides an alternative signal path. By introducing this intermediate structure at a different level, the patent enables signal routing that avoids the harmful electromagnetic interactions between closely spaced interconnection lines and contact plugs on the same plane.
2Area of stationary object
If the distances between conductive patterns are reduced, then the chip size decreases, but the parasitic capacitances between adjacent conductive patterns increase
Solution Approach 1:
The bypass interconnection line is positioned on a separate plane at a different level from the first and second interconnection lines. This three-dimensional arrangement allows the bypass line to provide alternative signal paths without increasing the footprint area, thereby reducing chip size while minimizing parasitic capacitance through spatial separation.
3Device complexity
If multiple interconnection lines are placed on the same plane, then the layout complexity is reduced, but the parasitic capacitances between lines increase
Solution Approach 1:
The patent segments the interconnection structure into multiple levels by placing the bypass interconnection line on a separate plane at a different level. This segmentation separates the signal paths spatially, reducing parasitic capacitance between the first and second interconnection lines while maintaining manageable layout complexity through systematic multi-level organization.
Solution Approach 2:
By transitioning from a single-plane to a multi-plane configuration, the patent adds a vertical dimension to the interconnection layout. This allows the bypass line to provide alternative routing paths without increasing horizontal layout complexity, as the additional routing capacity is achieved through vertical stacking rather than horizontal expansion.
Data Source
AI summary
A semiconductor device includes: a first interconnection line and a second interconnection line which extend apart from each other on a first plane at a first level on a substrate; a bypass interconnection line that extends on a second plane at a second level on the substrate; and a plurality of contact plugs for connecting the bypass interconnection line to the first interconnection line and the second interconnection line. A method includes forming a bypass interconnection line spaced apart from a substrate and forming on a same plane a plurality of interconnection lines connected to the bypass interconnection line via a plurality of contact plugs.